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Travelled to:
1 × Canada
1 × Mexico
1 × United Kingdom
14 × USA
Collaborated with:
H.Tseng B.Calder A.Venkat M.Kamruzzaman S.Swanson L.Porter W.Zhang N.Tuck A.Snavely G.R.Gao Mohammadkazem Taram V.Kontorinis H.Homayoun M.DeVuyst J.A.Brown B.Choi S.Wallace E.Tune D.Liang J.L.Lo S.J.Eggers H.M.Levy Sriskanda Shamasunder H.Shacham M.Arora S.Manne I.Paul N.Jayasena M.K.Tavana M.H.Hajkazemi A.Shayan T.Lin C.G.Quiñones C.Madriles F.J.Sánchez P.Marcuello A.González Fatemehsadat Mireshghallah Prakash Ramrakhyani A.Jalali H.Esmaeilzadeh
Talks about:
thread (9) multithread (4) processor (4) heterogen (4) predict (4) dynam (4) data (4) core (4) prefetch (3) trigger (3)

Person: Dean M. Tullsen

DBLP DBLP: Tullsen:Dean_M=

Contributed to:

HPCA 20152015
DAC 20142014
HPCA 20142014
ASPLOS 20122012
HPCA 20122012
OOPSLA 20122012
ASPLOS 20112011
HPCA 20112011
PLDI 20102010
ASPLOS 20082008
HPCA 20072007
CGO 20062006
HPCA 20052005
PLDI 20052005
HPCA 20012001
ASPLOS 20002000
HPCA 19991999
ASPLOS 20162016
ASPLOS 20192019
ASPLOS 20202020

Wrote 23 papers:

HPCA-2015-AroraMPJT #behaviour #benchmark #comprehension #cpu #gpu #metric #power management
Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems (MA, SM, IP, NJ, DMT), pp. 366–377.
DAC-2014-KontorinisTHTH
Enabling Dynamic Heterogeneity Through Core-on-Core Stacking (VK, MKT, MHH, DMT, HH), p. 6.
HPCA-2014-TsengT #named #thread
CDTT: Compiler-generated data-triggered threads (HWT, DMT), pp. 650–661.
ASPLOS-2012-DeVuystVT #execution #migration #multi
Execution migration in a heterogeneous-ISA chip multiprocessor (MD, AV, DMT), pp. 261–272.
HPCA-2012-HomayounKSLT #3d
Dynamically heterogeneous cores through 3D resource pooling (HH, VK, AS, TWL, DMT), pp. 323–334.
OOPSLA-2012-TsengT #thread
Software data-triggered threads (HWT, DMT), pp. 703–716.
ASPLOS-2011-KamruzzamanST #manycore #migration #thread #using
Inter-core prefetching for multicore processors using migrating helper threads (MK, SS, DMT), pp. 393–404.
HPCA-2011-BrownPT #concurrent #migration #performance #predict #set #thread
Fast thread migration via cache working set prediction (JAB, LP, DMT), pp. 193–204.
HPCA-2011-TsengT #thread
Data-triggered threads: Eliminating redundant computation (HWT, DMT), pp. 181–192.
PLDI-2010-KamruzzamanST #concurrent #distributed #performance #thread
Software data spreading: leveraging distributed caches to improve single thread performance (MK, SS, DMT), pp. 460–470.
ASPLOS-2008-ChoiPT #branch #predict #thread
Accurate branch prediction for short threads (BC, LP, DMT), pp. 125–134.
HPCA-2007-ZhangTC #adaptation #thread
Accelerating and Adapting Precomputation Threads for Effcient Prefetching (WZ, DMT, BC), pp. 85–95.
CGO-2006-ZhangCT #framework #optimisation #self
A Self-Repairing Prefetcher in an Event-Driven Dynamic Optimization Framework (WZ, BC, DMT), pp. 50–64.
HPCA-2005-TuckT #parallel #predict #thread
Multithreaded Value Prediction (NT, DMT), pp. 5–15.
PLDI-2005-QuinonesMSMGT #compilation #framework #slicing #thread
Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices (CGQ, CM, FJS, PM, AG, DMT), pp. 269–279.
HPCA-2001-TuneLTC #predict
Dynamic Prediction of Critical Path Instructions (ET, DL, DMT, BC), pp. 185–195.
ASPLOS-2000-SnavelyT #multi #thread
Symbiotic Jobscheduling for a Simultaneous Multithreading Processor (AS, DMT), pp. 234–244.
HPCA-1999-TullsenG #architecture #compilation #execution #parallel #thread
Multithreaded Execution Architecture and Compilation (DMT, GRG), p. 321.
HPCA-1999-TullsenLEL #fine-grained #multi #thread
Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor (DMT, JLL, SJE, HML), pp. 54–58.
HPCA-1999-WallaceTC #multi
Instruction Recycling on a Multiple-Path Processor (SW, DMT, BC), pp. 44–53.
ASPLOS-2016-VenkatSST #named
HIPStR: Heterogeneous-ISA Program State Relocation (AV, SS, HS, DMT), pp. 727–741.
ASPLOS-2019-TaramVT #execution
Context-Sensitive Fencing: Securing Speculative Execution via Microcode Customization (MT, AV, DMT), pp. 395–410.
ASPLOS-2020-MireshghallahTR #learning #named #privacy
Shredder: Learning Noise Distributions to Protect Inference Privacy (FM, MT, PR, AJ, DMT, HE), pp. 3–18.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.