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Travelled to:
1 × Canada
1 × Cyprus
1 × Estonia
1 × Hungary
1 × India
1 × Poland
1 × United Kingdom
12 × USA
2 × Germany
Collaborated with:
P.Sadayappan U.Bondhugula M.T.Kandemir M.M.Baskaran L.Pouchet A.Rountev S.Krishnamoorthy M.J.Irwin M.Narasimhan F.Rastello A.Hartono N.Vijaykrishnan I.Kadayif V.Elango T.Henretty A.N.Choudhary K.Stock C.Lam G.Baumgartner G.Chen J.Hong A.Narayan F.Franchetti S.Tavarageri N.Vydyanathan A.Parikh M.Ravishankar R.Dathathri M.Kong T.Grosser J.Shirako K.Sharma N.Fauzia V.Sarkar C.Bastoul A.Cohen N.Vasilache X.Gao S.K.Sahoo Q.Lu D.Cociorva M.Nooijen D.E.Bernholdt R.J.Harrison Changwan Hong Wenlei Bao A.C.0001
Talks about:
parallel (6) automat (6) optim (6) memori (5) comput (4) loop (4) data (4) architectur (3) transform (3) effect (3)

Person: J. Ramanujam

DBLP DBLP: Ramanujam:J=

Facilitated 1 volumes:

PPoPP 2012Ed

Contributed to:

POPL 20152015
PPoPP 20152015
PLDI 20142014
CC 20122012
CC 20112011
POPL 20112011
CC 20102010
CGO 20102010
PPoPP 20092009
CC 20082008
PLDI 20082008
PPoPP 20082008
PLDI 20072007
PPoPP 20072007
PPoPP 20052005
CC 20032003
DAC 20022002
PLDI 20022002
DAC 20012001
LCTES/OM 20012001
DAC 20002000
PLDI 20162016

Wrote 23 papers:

POPL-2015-ElangoRPRS #complexity #data access #on the #source code
On Characterizing the Data Access Complexity of Programs (VE, FR, LNP, JR, PS), pp. 567–580.
PPoPP-2015-RavishankarDEPRRS #code generation #distributed #memory management
Distributed memory code generation for mixed Irregular/Regular computations (MR, RD, VE, LNP, JR, AR, PS), pp. 65–75.
PLDI-2014-StockKGPRRS #framework #order #reuse
A framework for enhancing data reuse via associative reordering (KS, MK, TG, LNP, FR, JR, PS), p. 10.
CC-2012-ShirakoSFPRSS #bound
Analytical Bounds for Optimal Tile Size Selection (JS, KS, NF, LNP, JR, PS, VS), pp. 101–121.
CC-2011-HenrettySPFRS #architecture #layout
Data Layout Transformation for Stencil Computations on Short-Vector SIMD Architectures (TH, KS, LNP, FF, JR, PS), pp. 225–245.
POPL-2011-PouchetBBCRSV #optimisation
Loop transformations: convexity, pruning and optimization (LNP, UB, CB, AC, JR, PS, NV), pp. 549–562.
CC-2010-BaskaranRS #automation #code generation #source code
Automatic C-to-CUDA Code Generation for Affine Programs (MMB, JR, PS), pp. 244–263.
CGO-2010-BaskaranHTHRS #revisited
Parameterized tiling revisited (MMB, AH, ST, TH, JR, PS), pp. 200–209.
PPoPP-2009-BaskaranVBRRS #effectiveness #manycore #parallel #scheduling
Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors (MMB, NV, UB, JR, AR, PS), pp. 219–228.
CC-2008-BondhugulaBKRRS #automation #locality #optimisation #parallel
Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model (UB, MMB, SK, JR, AR, PS), pp. 132–146.
PLDI-2008-BondhugulaHRS #automation #locality
A practical automatic polyhedral parallelizer and locality optimizer (UB, AH, JR, PS), pp. 101–113.
PPoPP-2008-BaskaranBKRRS #architecture #automation #data flow #parallel
Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories (MMB, UB, SK, JR, AR, PS), pp. 1–10.
PLDI-2007-KrishnamoorthyBBRRS #automation #effectiveness #parallel
Effective automatic parallelization of stencil computations (SK, MMB, UB, JR, AR, PS), pp. 235–244.
PPoPP-2007-BondhugulaRS #automation
Automatic mapping of nested loops to FPGAS (UB, JR, PS), pp. 101–111.
PPoPP-2005-GaoSLRLBS #modelling #optimisation #parallel #performance
Performance modeling and optimization of parallel out-of-core tensor contractions (XG, SKS, CCL, JR, QL, GB, PS), pp. 266–276.
Address Register Assignment for Reducing Code Size (MTK, MJI, GC, JR), pp. 273–289.
DAC-2002-KandemirRC #embedded #memory management #multi
Exploiting shared scratch pad memory space in embedded multiprocessor systems (MTK, JR, ANC), pp. 219–224.
PLDI-2002-CociorvaBLSRNBH #optimisation #trade-off
Space-Time Trade-Off Optimization for a Class of Electronic Structure Calculations (DC, GB, CCL, PS, JR, MN, DEB, RJH), pp. 177–186.
DAC-2001-KandemirRIVKP #memory management
Dynamic Management of Scratch-Pad Memory Space (MTK, JR, MJI, NV, IK, AP), pp. 690–695.
DAC-2001-RamanujamHKN #embedded #memory management #requirements
Reducing Memory Requirements of Nested Loops for Embedded Systems (JR, JH, MTK, AN), pp. 359–364.
LCTES-OM-2001-KadayifKVIR #architecture
Morphable Cache Architectures: Potential Benefits (IK, MTK, NV, MJI, JR), pp. 128–137.
DAC-2000-NarasimhanR #bound #on the #problem #scheduling #synthesis
On lower bounds for scheduling problems in high-level synthesis (MN, JR), pp. 546–551.
PLDI-2016-HongB0KPRRS #array #effectiveness #multi
Effective padding of multidimensional arrays to avoid cache conflict misses (CH, WB, AC0, SK, LNP, FR, JR, PS), pp. 129–144.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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