Travelled to:2 × Germany
3 × USA
Collaborated with:J.Cong C.Liu W.Jiang Y.Zou P.Zhang M.Huang B.Xiao Y.Chen B.Liu M.Potkonjak G.Reinman
Talks about:level (2) cach (2) awar (2) scratchpad (1) reconfigur (1) increment (1) framework (1) algorithm (1) synthesi (1) recognit (1)
Person: Hui Huang
DBLP: Huang:Hui
Contributed to:
2015
2012201120102000Wrote 5 papers:
- DAC-2015-ZhangHXHC #compilation #framework #named
- CMOST: a system-level FPGA compilation framework (PZ, MH, BX, HH, JC), p. 6.
- DATE-2012-ChenCHLLPR #configuration management #design #energy #hybrid
- Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design (YTC, JC, HH, BL, CL, MP, GR), pp. 45–50.
- DAC-2011-CongHLZ #memory management
- A reuse-aware prefetching scheme for scratchpad memory (JC, HH, CL, YZ), pp. 960–965.
- DATE-2010-CongHJ #algorithm #behaviour #pattern matching #pattern recognition #recognition #synthesis
- A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis (JC, HH, WJ), pp. 1255–1260.
- DAC-2000-CongH #array #incremental #programmable
- Depth optimal incremental mapping for field programmable gate arrays (JC, HH), pp. 290–293.