Travelled to:1 × Germany
3 × France
Collaborated with:A.Rueda M.Martínez M.J.Avedillo J.M.Quintana E.J.Peralías A.J.Acosta D.Vázquez G.Leger G.Huertas J.A.Prieto I.A.Grout A.M.D.Richardson
Talks about:signal (2) design (2) analog (2) methodolog (1) constrain (1) algorithm (1) approach (1) testabl (1) realist (1) problem (1)
Person: José L. Huertas
DBLP: Huertas:Jos=eacute=_L=
Contributed to:
2004200019991998Wrote 5 papers:
- DATE-v1-2004-VazquezLHRH #parametricity #self
- A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test Applications (DV, GL, GH, AR, JLH), pp. 298–305.
- DATE-2000-PeraliasARH #design #pipes and filters #verification
- A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters (EJP, AJA, AR, JLH), pp. 534–538.
- DATE-1999-MartinezAQH #algorithm #encoding #using
- An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length (MM, MJA, JMQ, JLH), pp. 521–525.
- DATE-1998-MartinezAQH #problem
- A Dynamic Model for the State Assignment Problem (MM, MJA, JMQ, JLH), pp. 835–839.
- DATE-1998-PrietoRGPHR #approach #design #fault #layout #predict #testing
- An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits (JAP, AR, IAG, EJP, JLH, AMDR), pp. 905–909.