Travelled to:3 × France
Collaborated with:A.Raghunathan K.Roy A.A.Goud M.Sharad V.J.Kozhikkottu S.Dey S.Venkataramani X.Fong A.Ranjan S.G.Ramasubramanian V.S.Pai M.Pellauer Yakun Sophia Shao J.Clemons N.C.Crago Kartik Hegde S.W.Keckler C.W.Fletcher J.S.Emer
Talks about:effici (3) base (3) energi (2) domain (2) wall (2) spin (2) use (2) underlap (1) tapestri (1) spintast (1)
Person: Rangharajan Venkatesan
DBLP: Venkatesan:Rangharajan
Contributed to:
201520132011
2019Wrote 6 papers:
- DATE-2015-GoudVRR #design #robust #symmetry
- Asymmetric underlapped FinFET based robust SRAM design at 7nm node (AAG, RV, AR, KR), pp. 659–664.
- DATE-2015-RanjanRVPRR #configuration management #memory management #named #using
- DyReCTape: a dynamically reconfigurable cache using domain wall memory tapes (AR, SGR, RV, VSP, KR, AR), pp. 181–186.
- DATE-2015-VenkatesanVFRR #energy #logic #named
- Spintastic: spin-based stochastic logic for energy-efficient computing (RV, SV, XF, KR, AR), pp. 1575–1578.
- DATE-2013-VenkatesanSRR #energy #named #performance #using
- DWM-TAPESTRI — an energy efficient all-spin cache using domain wall shift based writes (RV, MS, KR, AR), pp. 1825–1830.
- DATE-2011-KozhikkottuVRD #analysis #named #performance #variability
- VESPA: Variability emulation for System-on-Chip performance analysis (VJK, RV, AR, SD), pp. 2–7.
- ASPLOS-2019-PellauerSCCHVKF #composition #distributed #named #performance
- Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration (MP, YSS, JC, NCC, KH, RV, SWK, CWF, JSE), pp. 137–151.