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Open Knowledge
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Travelled to:
1 × France
1 × United Kingdom
8 × USA
Collaborated with:
S.S.Mukherjee M.Pellauer H.Patil M.Adler A.Jaleel S.C.S.Jr. S.K.Reinhardt B.Calder D.Grunwald D.Chiou E.Borch E.Tune S.Manne J.Nuzman A.Moga H.H.Najaf-abadi S.Subramaniam M.A.Kinsy A.Parashar M.D.Powell A.Biswas B.R.Sheikh S.M.Yardi F.Silla P.J.Bannon S.Lang D.Webb Yakun Sophia Shao J.Clemons N.C.Crago Kartik Hegde R.Venkatesan S.W.Keckler C.W.Fletcher
Talks about:
cach (4) problem (2) predict (2) time (2) soft (2) high (2) use (2) architectur (1) multiplex (1) hierarchi (1)

Person: Joel S. Emer

DBLP DBLP: Emer:Joel_S=

Facilitated 1 volumes:


Contributed to:

HPCA 20152015
ASPLOS 20122012
HPCA 20112011
DAC 20092009
HPCA 20092009
HPCA 20052005
ASPLOS 20022002
HPCA 20022002
HPCA 20002000
HPCA 19961996
ASPLOS 20192019

Wrote 11 papers:

HPCA-2015-JaleelNMSE #latency
High performing cache hierarchies for server workloads: Relaxing inclusion to capture the latency benefits of exclusive caches (AJ, JN, AM, SCSJ, JSE), pp. 343–353.
ASPLOS-2012-JaleelNSSE #named #scheduling
CRUISE: cache replacement and utility-aware scheduling (AJ, HHNa, SS, SCSJ, JSE), pp. 249–260.
HPCA-2011-PellauerAKPE #manycore #named #simulation #using
HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing (MP, MA, MAK, AP, JSE), pp. 406–417.
DAC-2009-PellauerACE #composition #problem
Soft connections: addressing the hardware-design modularity problem (MP, MA, DC, JSE), pp. 276–281.
HPCA-2009-PowellBEMSY #named #parametricity #runtime #using
CAMP: A technique to estimate per-structure power at run-time using a few simple parameters (MDP, AB, JSE, SSM, BRS, SMY), pp. 289–300.
HPCA-2005-MukherjeeER #architecture #fault #perspective #problem
The Soft Error Problem: An Architectural Perspective (SSM, JSE, SKR), pp. 243–247.
ASPLOS-2002-MukherjeeSBELW #algorithm #case study #comparative #pipes and filters
A comparative study of arbitration algorithms for the Alpha 21364 pipelined router (SSM, FS, PJB, JSE, SL, DW), pp. 223–234.
Loose Loops Sink Chips (EB, ET, SM, JSE), pp. 299–310.
HPCA-2000-PatilE #alias #branch #predict
Combining Static and Dynamic Branch Prediction to Reduce Destructive Aliasing (HP, JSE), pp. 251–262.
HPCA-1996-CalderGE #predict
Predictive Sequential Associative Cache (BC, DG, JSE), pp. 244–253.
ASPLOS-2019-PellauerSCCHVKF #composition #distributed #named #performance
Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration (MP, YSS, JC, NCC, KH, RV, SWK, CWF, JSE), pp. 137–151.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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