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Travelled to:
3 × USA
Collaborated with:
A.Adir E.Bin S.Asaf L.Fournier I.Jaeger H.Azatchi K.Shoikhet A.Ghanayim K.Holtz E.Marcus R.Morad M.Rimon G.Shurek E.Tsanko
Talks about:
architectur (2) verif (2) microprocessor (1) processor (1) framework (1) complianc (1) approach (1) ontolog (1) hardwar (1) generic (1)

Person: Ofer Peled

DBLP DBLP: Peled:Ofer

Contributed to:

SEKE 20102010
DAC 20072007
DAC 20052005

Wrote 3 papers:

SEKE-2010-BinGHMMPRST #hardware #ontology #tool support #verification
Ontology-Based Tools in the Service of Hardware Verification (EB, AG, KH, EM, RM, OP, MR, GS, ET), pp. 303–308.
DAC-2007-AdirAFJP #architecture #framework #validation
A Framework for the Validation of Processor Architecture Compliance (AA, SA, LF, IJ, OP), pp. 902–905.
DAC-2005-AdirABPS #approach #architecture #testing #verification
A generic micro-architectural test plan approach for microprocessor verification (AA, HA, EB, OP, KS), pp. 769–774.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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