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Travelled to:
2 × Germany
2 × USA
Collaborated with:
P.Banerjee J.H.Patel N.Karimi K.Chakrabarty P.Gupta R.Vemu A.Jas J.A.Abraham R.Galivanche
Talks about:
generat (3) test (3) parallel (2) circuit (2) multiprocessor (1) processor (1) algorithm (1) techniqu (1) sequenti (1) general (1)

Person: Srinivas Patil

DBLP DBLP: Patil:Srinivas

Contributed to:

DATE 20122012
DATE 20082008
DAC 19911991
DAC 19891989

Wrote 4 papers:

DATE-2012-KarimiCGP #fault #generative #testing
Test generation for clock-domain crossing faults in integrated circuits (NK, KC, PG, SP), pp. 406–411.
DATE-2008-VemuJAPG #concurrent #detection #fault #logic #low cost
A low-cost concurrent error detection technique for processor control logic (RV, AJ, JAA, SP, RG), pp. 897–902.
DAC-1991-PatilBP #generative #parallel #testing
Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors (SP, PB, JHP), pp. 155–159.
DAC-1989-PatilB #algorithm #bound #branch #generative #parallel #testing
A Parallel Branch and Bound Algorithm for Test Generation (SP, PB), pp. 339–343.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.