Travelled to:1 × USA
2 × France
2 × Germany
Collaborated with:W.Kruijtzer H.W.M.v.Moll H.Corporaal M.Boonen W.H.Tibboel M.Klompstra D.Alders T.Bautista G.Alkadi A.Núñez P.J.Mosterman D.Orofino J.Sztipanovits A.A.Jerraya C.G.Cassandras G.Martin J.Castrillón L.Thiele L.Schor W.Sheng B.H.H.Juurlink M.A.Mesa A.Pohl R.Jessenberger R.Leupers
Talks about:system (3) model (3) level (3) function (2) design (2) protocol (1) program (1) environ (1) automat (1) specif (1)
Person: Víctor Reyes
DBLP: Reyes:V=iacute=ctor
Contributed to:
201520092008
20072006Wrote 5 papers:
- DATE-2015-CastrillonTSSJA #manycore #programming #question
- Multi/many-core programming: where are we standing? (JC, LT, LS, WS, BHHJ, MAM, AP, RJ, VR, RL), pp. 1708–1717.
- DATE-2009-MollCRB #modelling #performance #protocol #using
- Fast and accurate protocol specific bus modeling using TLM 2.0 (HWMvM, HC, VR, MB), pp. 316–319.
- DATE-2008-MostermanOSJKRCM #automation #embedded #functional #modelling
- Automatically Realising Embedded Systems from High-Level Functional Models (PJM, DO, JS, AAJ, WK, VR, CGC, GM).
- DAC-2007-TibboelRKA #design #functional
- System-Level Design Flow Based on a Functional Reference for HW and SW (WHT, VR, MK, DA), pp. 23–28.
- DATE-2006-ReyesKBAN #case study #design #modelling #simulation
- A unified system-level modeling and simulation environment for MPSoC design: MPEG-4 decoder case study (VR, WK, TB, GA, AN), pp. 474–479.