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Travelled to:
6 × Germany
9 × France
9 × USA
Collaborated with:
S.Yoo G.Nicolescu L.Gauthier A.Baghdadi P.Kission C.Liem P.G.Paulin A.Bouchhima G.Matheron D.Lyonnard S.Han S.Chae Y.Paviot D.Lattard R.Ernst M.Diaz-Nava I.Bacivarov M.Bonaciu M.Youssef W.O.Cesário X.Guerin W.Lafi F.Pétrot K.Svarstad A.Jemai H.Ding T.B.Ismail K.O'Brien M.Dziri F.R.Wagner F.Gharsalli S.Meftali F.Rousseau N.Zergainoh P.Varinot R.Jamier B.Courtois F.Dumitrascu L.Pieralisi A.Sasongko C.Jalier G.Sassatelli P.Benoit L.Torres P.J.Mosterman D.Orofino J.Sztipanovits W.Kruijtzer V.Reyes C.G.Cassandras G.Martin J.Borel S.Resve M.Rogers W.Rosenstiel I.Rugen-Herzig F.Theewen I.Moussa Z.Sugar R.Suescun M.Pavesi S.Crudo L.Gazi E.Berrebi S.Vernalde S.D.Troch J.Herluison J.Fréhel I.Bolsens M.Cornero M.Santana J.Gentit J.Lopez X.Figari L.Bergher K.Huang K.Popovici L.B.d.Brisolara L.Li X.Yan L.Carro
Talks about:
design (16) system (12) model (8) embed (7) architectur (6) applic (6) processor (5) abstract (5) automat (5) specif (5)

Person: Ahmed Amine Jerraya

DBLP DBLP: Jerraya:Ahmed_Amine

Contributed to:

DATE 20112011
DATE 20102010
DATE 20092009
DATE 20082008
DAC 20072007
DATE 20072007
DAC 20062006
DATE Designers’ Forum 20062006
DAC 20042004
DATE v2 20042004
DATE 20032003
DAC 20022002
DATE 20022002
DAC 20012001
DATE 20012001
DATE 20002000
DAC 19991999
DATE 19991999
DATE 19981998
DAC 19971997
ED&TC 19971997
DAC 19961996
DAC 19941994
EDAC-ETC-EUROASIC 19941994
DAC 19861986

Wrote 36 papers:

DATE-2011-LafiLJ #3d #configuration management #framework
A 3D reconfigurable platform for 4G telecom applications (WL, DL, AAJ), pp. 555–558.
DATE-2010-JalierLJSBT #mobile
Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem (CJ, DL, AAJ, GS, PB, LT), pp. 184–189.
DATE-2009-JerrayaN #comprehension #embedded #manycore #tutorial
Embedded tutorial — Understanding multicore technologies (AAJ, GN), p. 1051.
DATE-2008-MostermanOSJKRCM #automation #embedded #functional #modelling
Automatically Realising Embedded Systems from High-Level Functional Models (PJM, DO, JS, AAJ, WK, VR, CGC, GM).
DAC-2007-HuangHPBGLyCCJ #case study #design
Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264 (KH, SIH, KP, LBdB, XG, LL, XY, SIC, LC, AAJ), pp. 39–42.
DATE-2007-Jerraya #architecture #implementation #modelling
HW/SW implementation from abstract architecture models (AAJ), pp. 1470–1471.
DAC-2006-HanGCJ #memory management #optimisation #video
Buffer memory optimization for video codec application modeled in Simulink (SIH, XG, SIC, AAJ), pp. 689–694.
DAC-2006-JerrayaBP #abstraction #interface #modelling #multi #programming
Programming models and HW-SW interfaces abstraction for multi-processor SoC (AAJ, AB, FP), pp. 280–285.
DATE-DF-2006-DumitrascuBPBJ #flexibility #framework #performance #platform
Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application (FD, IB, LP, MB, AAJ), pp. 166–171.
DAC-2004-HanBBCJ #architecture #data transfer #distributed #flexibility #memory management #multi #performance #scalability
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory (SIH, AB, MB, SIC, AAJ), pp. 250–255.
DAC-2004-YoussefYSPJ #case study #debugging #design #interface #video
Debugging HW/SW interface for MPSoC: video encoder system design case study (MWY, SY, AS, YP, AAJ), pp. 908–913.
DATE-v2-2004-DziriCWJ #component #design #integration #multi #validation
Unified Component Integration Flow for Multi-Processor SoC Design and Validation (MAD, WOC, FRW, AAJ), pp. 1132–1137.
DATE-v2-2004-YooYBJD #concept #design #multi #using
Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software (SY, MWY, AB, AAJ, MDN), pp. 1382–1383.
DATE-2003-YooBBPJ #abstraction #hardware #modelling #performance #simulation
Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer (SY, IB, AB, YP, AAJ), pp. 10550–10555.
DATE-2003-YooJ #abstraction #hardware
Introduction to Hardware Abstraction Layers for SoC (SY, AAJ), pp. 10336–10337.
DAC-2002-CesarioBGLNPYJD #approach #component #design #manycore
Component-based design approach for multicore SoCs (WOC, AB, LG, DL, GN, YP, SY, AAJ, MDN), pp. 789–794.
DAC-2002-GharsalliMRJ #automation #embedded #generative #memory management #multi
Automatic generation of embedded memory wrapper for multiprocessor SoC (FG, SM, FR, AAJ), pp. 596–601.
DATE-2002-BorelMJRRRRT
MEDEA+ and ITRS Roadmaps (JB, GM, AAJ, SR, MR, WR, IRH, FT), p. 328.
DATE-2002-YooNGJ #automation #design #generative #modelling #operating system #performance #simulation
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design (SY, GN, LG, AAJ), pp. 620–627.
DAC-2001-LyonnardYBJ #architecture #automation #generative #multi
Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip (DL, SY, AB, AAJ), pp. 518–523.
DATE-2001-BaghdadiLZJ #architecture #design #multi #performance
An efficient architecture model for systematic design of application-specific multiprocessor SoC (AB, DL, NEZ, AAJ), pp. 55–63.
DATE-2001-GauthierYJ #automation #embedded #generative #operating system
Automatic generation and targeting of application specific operating systems and embedded systems software (LG, SY, AAJ), pp. 679–685.
DATE-2001-JerrayaM #design
Electronic system design methodology: Europe’s positioning (AAJ, GM), pp. 720–721.
DATE-2001-NicolescuYJ #communication #design #refinement
Mixed-level cosimulation for fine gradual refinement of communication in SoC design (GN, SY, AAJ), pp. 754–759.
DATE-2001-SvarstadNJ #communication #design #embedded #specification
A model for describing communication between aggregate objects in the specification and design of embedded systems (KS, GN, AAJ), pp. 77–85.
DATE-2000-GauthierJ #simulation
Cycle-True Simulation of the ST10 Microcontroller (LG, AAJ), p. 742.
DAC-1999-MoussaSSDPCGJ #behaviour #design
Comparing RTL and Behavioral Design Methodologies in the Case of a 2M-Transistor ATM Shaper (IM, ZS, RS, MDN, MP, SC, LG, AAJ), pp. 598–603.
DATE-1999-JerrayaE #design #multi
Multi-Language System Design (AAJ, RE), p. 696–?.
DATE-1998-JemaiKJ #architecture #behaviour #simulation #synthesis
Architectural Simulation in the Context of Behavioral Synthesis (AJ, PK, AAJ), pp. 590–595.
DAC-1997-LiemCSPJGLFB #case study #development #embedded #multi
Am Embedded System Case Study: The Firm Ware Development Environment for a Multimedia Audio Processor (CL, MC, MS, PGP, AAJ, JMG, JL, XF, LB), pp. 780–785.
EDTC-1997-LiemPJ #design #embedded #named
ReCode: the design and re-design of the instruction codes for embedded instruction-set processors (CL, PGP, AAJ), p. 612.
DAC-1996-BerrebiKVTHFJB #control flow #data flow #synthesis
Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis (EB, PK, SV, SDT, JCH, JF, AAJ, IB), pp. 573–578.
DAC-1996-LiemPJ #architecture #compilation
Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures (CL, PGP, AAJ), pp. 597–600.
DAC-1994-KissionDJ #design
Structured Design Methodology for High-Level Design (PK, HD, AAJ), pp. 466–471.
EDAC-1994-IsmailOJ #clustering #interactive
Interactive System-level Partitioning with PARTIF (TBI, KO, AAJ), pp. 464–468.
DAC-1986-JerrayaVJC #compilation
Principles of the SYCO compiler (AAJ, PV, RJ, BC), pp. 715–721.

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