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Travelled to:
1 × France
3 × USA
Collaborated with:
Y.Li P.Ampadu M.Zhang H.Hatamkhani F.Lambrecht C.K.Yang R.I.Bahar J.Dworak R.Weiss H.Fariborzi F.Chen R.Nathanael I.Chen L.Hutin R.Lee T.K.Liu
Talks about:
microprocessor (1) implement (1) algorithm (1) multicor (1) instruct (1) protect (1) circuit (1) centric (1) barrier (1) system (1)

Person: Vladimir Stojanovic

DBLP DBLP: Stojanovic:Vladimir

Contributed to:

DAC 20132013
DATE 20132013
DAC 20092009
DAC 20062006

Wrote 5 papers:

DAC-2013-FariborziCNCHLLS
Relays do not leak: CMOS does (HF, FC, RN, IRC, LH, RL, TJKL, VS), p. 4.
DATE-2013-AmpaduZS #energy #fault tolerance #manycore
Breaking the energy barrier in fault-tolerant caches for multicore systems (PA, MZ, VS), pp. 731–736.
DAC-2009-LiS #algorithm #optimisation #robust
Yield-driven iterative robust circuit optimization algorithm (YL, VS), pp. 599–604.
DAC-2006-HatamkhaniLSY #design #performance
Power-centric design of high-speed I/Os (HH, FL, VS, CKKY), pp. 867–872.
DAC-2006-StojanovicBDW #effectiveness #implementation #queue
A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors (VS, RIB, JD, RW), pp. 705–708.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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