Travelled to:2 × Germany
3 × France
4 × USA
Collaborated with:K.Nepal J.L.Mundy W.R.Patterson A.Zaslavsky J.Dworak T.Moreshet G.D.Hachtel F.Somenzi E.Macii K.Nepal Y.Li S.Reda N.Alves V.Stojanovic R.Weiss D.Tadesse D.Sheffield E.Lenge J.Grodstein H.Cho S.Manne A.Pardo M.Poncino
Talks about:circuit (6) design (4) comput (3) use (3) techniqu (2) instruct (2) analysi (2) combin (2) queue (2) power (2)
Person: R. Iris Bahar
DBLP: Bahar:R=_Iris
Contributed to:
201420092007
200620062005200319951994Wrote 10 papers:
- DATE-2014-NepalLBR #approximate #automation #behaviour #named #synthesis
- ABACUS: A technique for automated behavioral synthesis of approximate computing circuits (KN, YL, RIB, SR), pp. 1–6.
- DATE-2009-AlvesNDB #detection #fault #multi #using
- Detecting errors using multi-cycle invariance information (NA, KN, JD, RIB), pp. 791–796.
- DATE-2007-NepalBMPZ #design #interactive #multi
- Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits (KN, RIB, JLM, WRP, AZ), pp. 576–581.
- DATE-2007-TadesseSLBG #analysis #modelling #satisfiability #using
- Accurate timing analysis using SAT and pattern-dependent delay models (DT, DS, EL, RIB, JG), pp. 1018–1023.
- DAC-2006-StojanovicBDW #effectiveness #implementation #queue
- A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors (VS, RIB, JD, RW), pp. 705–708.
- DATE-2006-NepalBMPZ #design #fault #memory management
- Designing MRF based error correcting circuits for memory elements (KN, RIB, JLM, WRP, AZ), pp. 792–793.
- DAC-2005-NepalBMPZ #design #logic #probability
- Designing logic circuits for probabilistic computation in the presence of noise (KN, RIB, JLM, WRP, AZ), pp. 485–490.
- DAC-2003-MoreshetB #design #power management #queue
- Power-aware issue queue design for speculative instructions (TM, RIB), pp. 634–637.
- DAC-1995-MannePBHSMP
- Computing the Maximum Power Cycles of a Sequential Circuit (SM, AP, RIB, GDH, FS, EM, MP), pp. 23–28.
- EDAC-1994-BaharCHMS #analysis #using
- Timing Analysis of Combinational Circuits using ADD’s (RIB, HC, GDH, EM, FS), pp. 625–629.