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Travelled to:
1 × France
7 × USA
Collaborated with:
X.Zhao L.Han P.Li Z.Zeng Y.Zhan P.Gundecha S.Ranganath H.Liu X.Ye Y.Guo S.Hu G.Yu W.Dong
Talks about:
analysi (5) parallel (4) circuit (4) simul (4) power (4) spice (3) grid (3) chip (3) gpu (3) statist (2)

Person: Zhuo Feng

DBLP DBLP: Feng:Zhuo

Contributed to:

DAC 20152015
DAC 20132013
DATE 20132013
KDD 20132013
DAC 20122012
DAC 20112011
DAC 20102010
DAC 20072007

Wrote 12 papers:

DAC-2015-HanF #analysis #approach #cpu #gpu #graph #scalability
Transient-simulation guided graph sparsification approach to scalable harmonic balance (HB) analysis of post-layout RF circuits leveraging heterogeneous CPU-GPU computing systems (LH, ZF), p. 6.
DAC-2013-Feng #grid #power management #scalability #verification
Scalable vectorless power grid current integrity verification (ZF), p. 8.
DAC-2013-HanZF #gpu #named #parallel #simulation
TinySPICE: a parallel SPICE simulator on GPU for massively repeated small circuit simulations (LH, XZ, ZF), p. 8.
DATE-2013-Feng #geometry #grid #power management #reduction #scalability
Large-scale flip-chip power grid reduction with geometric templates (ZF), pp. 1679–1682.
KDD-2013-GundechaRFL #social #social media
A tool for collecting provenance data in social media (PG, SR, ZF, HL), pp. 1462–1465.
DAC-2012-ZhaoF #on the fly #performance #simulation #towards
Towards efficient SPICE-accurate nonlinear circuit simulation with on-the-fly support-circuit preconditioners (XZ, ZF), pp. 1119–1124.
DAC-2011-ZhaoF #3d #gpu #parallel #performance #platform
Fast multipole method on GPU: tackling 3-D capacitance extraction on massively parallel SIMD platforms (XZ, ZF), pp. 558–563.
DAC-2010-FengZ #analysis #grid #parallel #power management #robust
Parallel multigrid preconditioning on graphics processing units (GPUs) for robust power grid analysis (ZF, ZZ), pp. 661–666.
DAC-2010-ZengYFL #analysis #network #optimisation #power management #trade-off
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation (ZZ, XY, ZF, PL), pp. 831–836.
DAC-2010-ZhaoGFH #optimisation #parallel
Parallel hierarchical cross entropy optimization for on-chip decap budgeting (XZ, YG, ZF, SH), pp. 843–848.
DAC-2007-FengLZ #analysis #higher-order #parametricity #performance #reduction #statistics #using
Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction (ZF, PL, YZ), pp. 244–249.
DAC-2007-YuDFL #analysis #framework #nondeterminism #process #statistics
A Framework for Accounting for Process Model Uncertainty in Statistical Static Timing Analysis (GY, WD, ZF, PL), pp. 829–834.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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