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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × China
1 × Turkey
3 × USA
Collaborated with:
J.D.Davis F.Yu L.Zhang K.Asanovic D.A.Patterson J.D.Ellithorpe R.H.Katz Z.Qian X.Chen A.Waterman R.Avizienis Y.Lee H.Cook
Talks about:
architectur (2) network (2) hardwar (2) acceler (2) simul (2) fpgas (2) use (2) multiprocessor (1) reconfigur (1) warehous (1)

Person: Zhangxi Tan

DBLP DBLP: Tan:Zhangxi

Contributed to:

ASPLOS 20152015
DAC 20102010
DAC 20092009
DAC 20082008
SAT 20082008

Wrote 5 papers:

ASPLOS-2015-TanQCAP #named #network #using
DIABLO: A Warehouse-Scale Computer Network Simulator using FPGAs (ZT, ZQ, XC, KA, DAP), pp. 207–221.
DAC-2010-TanWALCPA #architecture #multi
RAMP gold: an FPGA-based architecture simulator for multiprocessors (ZT, AW, RA, YL, HC, DAP, KA), pp. 463–468.
DAC-2009-EllithorpeTK #architecture #named #network #using
Internet-in-a-Box: emulating datacenter network architectures using FPGAs (JDE, ZT, RHK), pp. 880–883.
DAC-2008-DavisTYZ #configuration management #hardware #satisfiability
A practical reconfigurable hardware accelerator for Boolean satisfiability solvers (JDD, ZT, FY, LZ), pp. 780–785.
SAT-2008-DavisTYZ #design #hardware #performance #satisfiability
Designing an Efficient Hardware Implication Accelerator for SAT Solving (JDD, ZT, FY, LZ), pp. 48–62.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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