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Travelled to:
1 × France
3 × USA
Collaborated with:
S.X.Tan H.Li A.C.Cabe M.R.Stan W.Guo L.Wu Y.Cai X.Hong J.Wang S.N.Wooters T.N.Blalock B.H.Calhoun
Talks about:
hierarch (2) approach (2) circuit (2) analog (2) sram (2) larg (2) base (2) standbi (1) analysi (1) system (1)

Person: Zhenyu Qi

DBLP DBLP: Qi:Zhenyu

Contributed to:

DAC 20102010
DAC 20052005
DAC 20042004
DATE v1 20042004

Wrote 5 papers:

DAC-2010-CabeQS #power management
Stacking SRAM banks for ultra low power standby mode operation (ACC, ZQ, MRS), pp. 699–704.
DAC-2010-QiWCWBCS #design
SRAM-based NBTI/PBTI sensor system design (ZQ, JW, ACC, SNW, TNB, BHC, MRS), pp. 849–852.
DAC-2005-LiQTWCH #approach #clustering #performance
Partitioning-based approach to fast on-chip decap budgeting and minimization (HL, ZQ, SXDT, LW, YC, XH), pp. 170–175.
DAC-2004-TanGQ #analysis #approach #scalability
Hierarchical approach to exact symbolic analysis of large analog circuits (SXDT, WG, ZQ), pp. 860–863.
DATE-v1-2004-TanQL #modelling #scalability #simulation
Hierarchical Modeling and Simulation of Large Analog Circuits (SXDT, ZQ, HL), pp. 740–741.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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