BibSLEIGH — Sheldon_X-D

Travelled to:

11 × USA
3 × Germany
4 × France

Collaborated with:

X.Liu H.Wang Z.Qi B.McGaughy R.Shen Y.Cai H.Yu X.Hong H.Li C.R.Shi V.Sukharev X.Huang B.Yan P.Liu X.Wang J.Xiong D.Li R.L.Lysecky F.Vahid W.Guo T.Kim T.Yu S.Swarup A.Gupta Z.Hao G.Shi H.Chen T.J.A.Eguia E.H.Pacheco M.Tirumala J.Relles L.Zhou J.Chen J.Fan N.Mi W.Wu L.Jin J.Yang L.Wu J.Shi W.Hou L.Ma P.Ho T.Wei S.Park Q.Zhu N.Chang S.Ula M.Maasoumy

Talks about:

power (9) analysi (8) circuit (7) model (7) network (5) analog (4) order (4) base (4) microprocessor (3) interconnect (3)

Person: Sheldon X.-D. Tan

DBLP: Tan:Sheldon_X==D=

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2001

Wrote 23 papers:

DAC-2015-ChenTSHK #analysis #modelling #multi #reliability: Interconnect reliability modeling and analysis for multi-branch interconnect trees (HBC, SXDT, VS, XH, TK), p. 6.
DAC-2014-HuangYST #assessment #grid #network #power management: Physics-based Electromigration Assessment for Power Grid Networks (XH, TY, VS, SXDT), p. 6.
DAC-2014-WeiKPZTCUM #energy: Battery Management and Application for Energy-Efficient Buildings (TW, TK, SP, QZ, SXDT, NC, SU, MM), p. 6.
DATE-2013-WangTSL #algorithm: A power-driven thermal sensor placement algorithm for dynamic thermal management (HW, SXDT, SS, XL), pp. 1215–1220.
DATE-2012-LiuTW #analysis #approach #graph #parallel #statistics: Parallel statistical analysis of analog circuits by GPU-accelerated graph-based approach (XL, SXDT, HW), pp. 852–857.
DATE-2012-LiuTWY #simulation: A GPU-accelerated envelope-following method for switching power converter simulation (XL, SXDT, HW, HY), pp. 1349–1354.
DATE-2012-WangTLG #runtime: Runtime power estimator calibration for high-performance microprocessors (HW, SXDT, XL, AG), pp. 352–357.
DAC-2011-HaoTSS #analysis #bound #performance #process: Performance bound analysis of analog circuits considering process variations (ZH, SXDT, RS, GS), pp. 310–315.
DAC-2010-LiuYT #algorithm #analysis #performance #robust #scalability: A robust periodic arnoldi shooting algorithm for efficient analysis of large-scale RF/MM ICs (XL, HY, SXDT), pp. 573–578.
DAC-2010-ShenTX #algorithm #analysis #correlation #linear #power management #statistics: A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation (RS, SXDT, JX), pp. 481–486.
DATE-2010-EguiaTSPT #behaviour #design #manycore #modelling: General behavioral thermal modeling and characterization for multi-core microprocessor design (TJAE, SXDT, RS, EHP, MT), pp. 1136–1141.
DAC-2009-ShiCHMTHW #analysis #gpu #grid #network #performance #power management: GPU friendly fast Poisson solver for structured power grid network analysis (JS, YC, WH, LM, SXDT, PHH, XW), pp. 178–183.
DATE-2009-WangCTHR #modelling #optimisation #performance #polynomial #using: An efficient decoupling capacitance optimization using piecewise polynomial models (XW, YC, SXDT, XH, JR), pp. 1190–1195.
DAC-2008-YanZTCM #distributed #linear #named #network #order #reduction: DeMOR: decentralized model order reduction of linear networks with massive ports (BY, LZ, SXDT, JC, BM), pp. 409–414.
DATE-2008-LiTM #analysis #grid #named #network #power management: ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis (DL, SXDT, BM), pp. 432–437.
DAC-2007-YanTLM #higher-order #named #reduction: SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits (BY, SXDT, PL, BM), pp. 158–161.
DATE-2007-FanMTCH #correlation #order #reduction #statistics: Statistical model order reduction for interconnect circuits considering spatial correlations (JF, NM, SXDT, YC, XH), pp. 1508–1513.
DAC-2006-WuJYLT #estimation #functional: A systematic method for functional unit power estimation in microprocessors (WW, LJ, JY, PL, SXDT), pp. 554–557.
DAC-2005-LiQTWCH #approach #clustering #performance: Partitioning-based approach to fast on-chip decap budgeting and minimization (HL, ZQ, SXDT, LW, YC, XH), pp. 170–175.
DAC-2004-LyseckyVT #compilation: Dynamic FPGA routing for just-in-time FPGA compilation (RLL, FV, SXDT), pp. 954–959.
DAC-2004-TanGQ #analysis #approach #scalability: Hierarchical approach to exact symbolic analysis of large analog circuits (SXDT, WG, ZQ), pp. 860–863.
DATE-v1-2004-TanQL #modelling #scalability #simulation: Hierarchical Modeling and Simulation of Large Analog Circuits (SXDT, ZQ, HL), pp. 740–741.
DAC-2001-TanS #modelling #network #optimisation #performance: Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling (SXDT, CJRS), pp. 550–554.