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Travelled to:
1 × Germany
2 × France
6 × USA
Collaborated with:
X.Hong S.X.Tan H.Yao T.Ho Q.Zhou J.Hu X.Wang Y.Ma S.Dong C.Cheng J.Gu F.Yang Q.Wang Y.Shen J.Relles J.Fan N.Mi H.Li Z.Qi L.Wu J.Shi W.Hou L.Ma P.Ho Y.Lu C.C.N.Sze L.Huang S.Chen
Talks about:
base (5) block (3) microfluid (2) constraint (2) practic (2) network (2) biochip (2) analysi (2) shape (2) optim (2)

Person: Yici Cai


Contributed to:

DAC 20152015
DAC 20142014
DATE 20102010
DAC 20092009
DATE 20092009
DATE 20072007
DAC 20052005
DAC 20032003
DAC 20012001

Wrote 10 papers:

DAC-2015-YaoHC #constraints #named
PACOR: practical control-layer routing flow with length-matching constraint for flow-based microfluidic biochips (HY, TYH, YC), p. 6.
DAC-2014-WangSYHC #functional
Practical Functional and Washing Droplet Routing for Cross-Contamination Avoidance in Digital Microfluidic Biochips (QW, YS, HY, TYH, YC), p. 6.
DATE-2010-YangCZH #multi #satisfiability
SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal (FY, YC, QZ, JH), pp. 1369–1372.
DAC-2009-ShiCHMTHW #analysis #gpu #grid #network #performance #power management
GPU friendly fast Poisson solver for structured power grid network analysis (JS, YC, WH, LM, SXDT, PHH, XW), pp. 178–183.
DATE-2009-WangCTHR #modelling #optimisation #performance #polynomial #using
An efficient decoupling capacitance optimization using piecewise polynomial models (XW, YC, SXDT, XH, JR), pp. 1190–1195.
DATE-2007-FanMTCH #correlation #order #reduction #statistics
Statistical model order reduction for interconnect circuits considering spatial correlations (JF, NM, SXDT, YC, XH), pp. 1508–1513.
DAC-2005-LiQTWCH #approach #clustering #performance
Partitioning-based approach to fast on-chip decap budgeting and minimization (HL, ZQ, SXDT, LW, YC, XH), pp. 170–175.
DAC-2005-LuSHZCHH #navigation #network
Navigating registers in placement for clock network minimization (YL, CCNS, XH, QZ, YC, LH, JH), pp. 176–181.
DAC-2003-MaHDCCCG #analysis #optimisation
Dynamic global buffer planning optimization based on detail block locating and congestion analysis (YM, XH, SD, SC, YC, CKC, JG), pp. 806–811.
DAC-2001-MaHDCCG #constraints
Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List (YM, XH, SD, YC, CKC, JG), pp. 770–775.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.