Person: Zhonghai Lu

DBLP: Lu:Zhonghai

Contributed to:

2015

2014

2012

2010

2009

2007

2003

Wrote 12 papers:

PDP-2015-MaZLZ #implementation #mvc

Implementing MVC Decoding on Homogeneous NoCs: Circuit Switching or Wormhole Switching (NM, ZZ, ZL, LRZ), pp. 387–391.

DATE-2014-LiuJL #parallel

Parallel probe based dynamic connection setup in TDM NoCs (SL, AJ, ZL), pp. 1–6.

DATE-2014-LongLY #analysis #bound #evaluation #modelling #multi

Analysis and evaluation of per-flow delay bound for multiplexing models (YL, ZL, XY), pp. 1–4.

DATE-2014-ZhaoL #bound

Empowering study of delay bound tightness with simulated annealing (XZ, ZL), pp. 1–6.

DATE-2012-JafariJL #analysis #scheduling #worst-case

Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling (FJ, AJ, ZL), pp. 538–541.

DATE-2012-LiuJL #constant #parallel

Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC (SL, AJ, ZL), pp. 1289–1294.

DATE-2010-ChenLJC #distributed #manycore #memory management #using

Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller (XC, ZL, AJ, SC), pp. 39–44.

DATE-2010-JafariLJY

Optimal regulation of traffic flows in networks-on-chip (FJ, ZL, AJ, MHY), pp. 1621–1624.

DATE-2010-LiuLKJ #adaptation #correlation #multi

FPGA-based adaptive computing for correlated multi-stream processing (ML, ZL, WK, AJ), pp. 973–976.

DATE-2009-LuMJBWH #communication

Flow regulation for on-chip communication (ZL, MM, AJ, ACB, PvdW, TH), pp. 578–581.

DAC-2007-LuLJ #network

Layered Switching for Networks on Chip (ZL, ML, AJ), pp. 122–127.

DATE-2003-SanderJL #design #development

Development and Application of Design Transformations in ForSyDe (IS, AJ, ZL), pp. 10364–10369.