BibSLEIGH — Axel

Travelled to:

4 × USA
5 × France
6 × Germany

Collaborated with:

Z.Lu I.Sander J.Öberg M.Millberg A.K.Deb P.Bjuréus S.Liu J.Zhu F.Jafari M.Liu E.Nilsson M.O'Nils R.Ma Z.Hui S.Kumar A.Hemani X.Chen S.Chen M.H.Yaghmaee W.Kuehn E.Villar C.Grimm T.Kogel T.Raudvere A.K.Singh R.Thid X.Zhang M.Ebrahimi L.Huang G.Li A.C.Bruce P.v.d.Wolf T.Henriksson Amir M. Rahmani Bryan Donyanavard Tiago Mück Kasra Moazzemi O.Mutlu N.D.Dutt I.A.Khatib F.Poletti D.Bertozzi L.Benini M.Bechara H.Khalifeh R.Nabiev

Talks about:

system (11) chip (8) network (7) design (6) applic (5) flow (5) use (5) analysi (4) stream (4) model (4)

Person: Axel Jantsch

DBLP: Jantsch:Axel

Contributed to:

2015

2014

2012

2010

2009

2008

2007

2006

2004

2003

2002

2000

1999

2018

Wrote 28 papers:

DATE-2015-MaHJ #manycore: A packet-switched interconnect for many-core systems with BE and RT service (RM, ZH, AJ), pp. 980–983.
PDP-2015-ZhangEHLJ #detection #fault: A Routing-Level Solution for Fault Detection, Masking, and Tolerance in NoCs (XZ, ME, LH, GL, AJ), pp. 365–369.
DATE-2014-LiuJL #parallel: Parallel probe based dynamic connection setup in TDM NoCs (SL, AJ, ZL), pp. 1–6.
DATE-2012-JafariJL #analysis #scheduling #worst-case: Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling (FJ, AJ, ZL), pp. 538–541.
DATE-2012-LiuJL #constant #parallel: Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC (SL, AJ, ZL), pp. 1289–1294.
DATE-2010-ChenLJC #distributed #manycore #memory management #using: Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller (XC, ZL, AJ, SC), pp. 39–44.
DATE-2010-JafariLJY: Optimal regulation of traffic flows in networks-on-chip (FJ, ZL, AJ, MHY), pp. 1621–1624.
DATE-2010-LiuLKJ #adaptation #correlation #multi: FPGA-based adaptive computing for correlated multi-stream processing (ML, ZL, WK, AJ), pp. 973–976.
DATE-2010-ZhuSJ #configuration management #cpu #design #performance #streaming: Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs (JZ, IS, AJ), pp. 1035–1040.
DATE-2009-LuMJBWH #communication: Flow regulation for on-chip communication (ZL, MM, AJ, ACB, PvdW, TH), pp. 578–581.
DATE-2009-MillbergJ #worst-case: Priority based forced requeue to reduce worst-case latencies for bursty traffic (MM, AJ), pp. 1070–1075.
DATE-2009-ZhuSJ #architecture #cpu #hybrid #realtime #scheduling #streaming: Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures (JZ, IS, AJ), pp. 1506–1511.
DATE-2008-VillarJGK #specification #using: Heterogeneous System-level Specification Using SystemC (EV, AJ, CG, TK).
DAC-2007-LuLJ #network: Layered Switching for Networks on Chip (ZL, ML, AJ), pp. 122–127.
DAC-2006-KhatibPBBBKJN #analysis #architecture #design #monitoring #multi #realtime: A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration (IAK, FP, DB, LB, MB, HK, AJ, RN), pp. 125–130.
DAC-2004-DebJO #design #modelling #paradigm #transaction: System design for DSP applications in transaction level modeling paradigm (AKD, AJ, JÖ), pp. 466–471.
DATE-v1-2004-DebJO #design #using: System Design for DSP Applications Using the MASIC Methodology (AKD, AJ, JÖ), pp. 630–635.
DATE-v1-2004-RaudvereSSJ #abstraction #polynomial #verification: Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits (TR, AKS, IS, AJ), pp. 690–691.
DATE-v2-2004-MillbergNTJ #network #using: Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip (MM, EN, RT, AJ), pp. 890–895.
DATE-2003-DebOJ #analysis #embedded #simulation #using: Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology (AKD, JÖ, AJ), pp. 11100–11101.
DATE-2003-NilssonMOJ #network #proximity: Load Distribution with the Proximity Congestion Awareness in a Network on Chip (EN, MM, JÖ, AJ), pp. 11126–11127.
DATE-2003-SanderJL #design #development: Development and Application of Design Transformations in ForSyDe (IS, AJ, ZL), pp. 10364–10369.
DAC-2002-SanderJ #communication #design #refinement: Transformation based communication and clock domain refinement for system design (IS, AJ), pp. 281–286.
DATE-2000-BjureusJ #control flow #named #specification: MASCOT: A Specification and Cosimulation Method Integrating Data and Control Flow (PB, AJ), pp. 161–168.
DATE-2000-JantschB: Composite Signal Flow: A Computational Model Combining Events, Sampled Streams, and Vectors (AJ, PB), pp. 154–160.
DATE-1999-JantschKH #analysis #case study #concept #modelling #synthesis: The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems (AJ, SK, AH), pp. 256–262.
DATE-1999-ONilsJ #implementation #independence #operating system #protocol #specification #synthesis: Operating System Sensitive Device Driver Synthesis from Implementation Independent Protocol Specification (MO, AJ), pp. 562–567.
ASPLOS-2018-RahmaniDMMJMD #coordination #manycore #named #resource management: SPECTR: Formal Supervisory Control and Coordination for Many-core Systems Resource Management (AMR, BD, TM, KM, AJ, OM, NDD), pp. 169–183.