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test (29)
design (13)
architectur (8)
optim (7)
use (7)

Stem soc$ (all stems)

52 papers:

PPDPPPDP-2015-Al-HumaimeedyF #multi #specification #verification
Enhancing the specification and verification techniques of multiparty sessions in SOC (ASAH, MF), pp. 19–30.
HTHT-2014-LacicKT #named #online #recommendation #scalability #social
SocRecM: a scalable social recommender engine for online marketplaces (EL, DK, CT), pp. 308–310.
DATEDATE-2012-RichterC #manycore #reduction
Test pin count reduction for NoC-based Test delivery in multicore SOCs (MR, KC), pp. 787–792.
KDDKDD-2012-ZhongFWXL #adaptation #behaviour #named #network #social
ComSoc: adaptive transfer of user behaviors over composite social network (EZ, WF, JW, LX, YL), pp. 696–704.
DACDAC-2010-Mathewson #evolution #how
The evolution of SOC interconnect and how NOC fits within it (BM), pp. 312–313.
DATEDATE-2009-SinhaRBS #design #multi #protocol #using
Multi-clock Soc design using protocol conversion (RS, PSR, SB, ZS), pp. 123–128.
PEPMPEPM-2009-LeuschelLOST #csp #named #slicing #specification
SOC: a slicer for CSP specifications (ML, ML, JO, JS, ST), pp. 165–168.
ICALPICALP-v2-2009-PuglieseTY #on the
On Observing Dynamic Prioritised Actions in SOC (RP, FT, NY), pp. 558–570.
SACSAC-2009-ThanheiserLS #approach #assessment #named #simulation
SimSOA: an approach for agent-based simulation and design-time assessment of SOC-based IT systems (ST, LL, HS), pp. 2162–2169.
DACDAC-2008-RajaramP #design #robust #synthesis
Robust chip-level clock tree synthesis for SOC designs (AR, DZP), pp. 720–723.
DATEDATE-2008-LarssonLCEP #architecture #optimisation #scheduling
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns (AL, EL, KC, PE, ZP), pp. 188–193.
DATEDATE-2008-SinanogluM #analysis #composition #reduction #testing
Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing (OS, EJM), pp. 182–187.
DACDAC-2007-AhmedTJ #design #fault #generative
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design (NA, MT, VJ), pp. 533–538.
DACDAC-2007-BhatiaGTMM #equivalence #multi #performance #validation
Leveraging Semi-Formal and Sequential Equivalence Techniques for Multimedia SOC Performance Validation (LB, JG, PT, RSM, SHM), pp. 69–74.
DACDAC-2007-XuZC #architecture #fault #optimisation
SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects (QX, YZ, KC), pp. 676–681.
DATEDATE-2007-LarssonLEP #integration #testing
Optimized integration of test compression and sharing for SOC testing (AL, EL, PE, ZP), pp. 207–212.
ICSMEICSM-2007-WuHH #empirical #evolution
Empirical Evidence for SOC Dynamics in Software Evolution (JW, RCH, AEH), pp. 244–254.
DACDAC-2006-ChangSC #design #evaluation #trade-off
Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs (KCC, JSS, TFC), pp. 143–148.
DACDAC-2006-NieuwoudtRM #named #optimisation #synthesis
SOC-NLNA: synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiers (AN, TR, YM), pp. 879–884.
DACDAC-2006-WangLLYHWH #design #framework #network #security
A network security processor design based on an integrated SOC design and test platform (CHW, CYL, MSL, JCY, CTH, CWW, SYH), pp. 490–495.
DATEDATE-2006-ChakrapaniACKPS #architecture #embedded #probability
Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology (LNC, BESA, SC, PK, KVP, BS), pp. 1110–1115.
DATEDATE-2006-ZengI #concurrent #testing #using
Concurrent core test for SOC using shared test set and scan chain disable (GZ, HI), pp. 1045–1050.
HPCAHPCA-2006-Emma #capacity #evolution #industrial
Industrial Perspectives: The Next Roadblocks in SOC Evolution: On-Chip Storage Capacity and Off-Chip Bandwidth (PGE), p. 201.
DATEDATE-2005-ChenLL #integration #layout #multi #verification
Integration, Verification and Layout of a Complex Multimedia SOC (CLC, JYL, YLL), pp. 1116–1117.
DATEDATE-2005-GoossensDGPRR #design #network #performance #verification
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification (KG, JD, OPG, SGP, AR, ER), pp. 1182–1187.
DATEDATE-2005-SehgalLOC #testing
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores (AS, FL, SO, KC), pp. 50–55.
DATEDATE-2005-Wu #testing
SOC Testing Methodology and Practice (CWW), pp. 1120–1121.
DACDAC-2004-RowenL #architecture #flexibility
Flexible architectures for engineering successful SOCs (CR, SL), pp. 692–697.
DACDAC-2004-Shanbhag #design #paradigm #reliability
A communication-theoretic design paradigm for reliable SOCs (NRS), p. 76.
DATEDATE-DF-2004-VorisekKF #testing
At-Speed Testing of SOC ICs (VV, TK, HF), pp. 120–125.
DATEDATE-v1-2004-SehgalC #architecture #composition #performance #testing #using
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures (AS, KC), pp. 422–427.
DACDAC-2003-HuangC #embedded #framework #using #verification
Using embedded infrastructure IP for SOC post-silicon verification (YH, WTC), pp. 674–677.
DACDAC-2003-SehgalIKC #multi #reduction #using
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers (AS, VI, MDK, KC), pp. 738–743.
DATEDATE-2003-GoelM #architecture #design
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization (SKG, EJM), pp. 10738–10741.
DATEDATE-2003-IyengarCSC #approach #optimisation #testing #using
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization (VI, AC, SS, KC), pp. 11188–11190.
DATEDATE-2003-MoullecADAP #metric #multi #personalisation
Multi-Granularity Metrics for the Era of Strongly Personalized SOCs (YLM, NBA, JPD, MA, JLP), pp. 10674–10681.
DACDAC-2002-ChandraC #reduction #testing #using
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes (AC, KC), pp. 673–678.
DACDAC-2002-IyengarCM #constraints #reduction #scheduling
Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs (VI, KC, EJM), pp. 685–690.
DACDAC-2002-KayCM #embedded
Embedded test control schemes for compression in SOCs (DK, SC, SM), pp. 679–684.
DACDAC-2002-KoukabDD #analysis #named #performance
HSpeedEx: a high-speed extractor for substrate noise analysis in complex mixed signal SOC (AK, CD, MJD), pp. 767–770.
DACDAC-2002-LeeP #analysis #design #embedded #performance #simulation
Timed compiled-code simulation of embedded software for performance analysis of SOC design (JYL, ICP), pp. 293–298.
DACDAC-2002-Zorian #framework
Embedding infrastructure IP for SOC yield improvement (YZ), pp. 709–712.
DATEDATE-2002-IyengarCM #performance #scalability
Efficient Wrapper/TAM Co-Optimization for Large SOCs (VI, KC, EJM), pp. 491–498.
DATEDATE-2002-KoranneC #network #problem #scheduling
Formulation of SOC Test Scheduling as a Network Transportation Problem (SK, VSC), p. 1125.
DATEDATE-2002-LeeLFCH #problem
A New Formulation for SOC Floorplan Area Minimization Problem (CHL, YCL, WYF, CCC, TMH), p. 1100.
DATEDATE-2002-LvWHL #adaptation #encoding #taxonomy
An Adaptive Dictionary Encoding Scheme for SOC Data Buses (TL, WW, JH, HL), pp. 1059–1064.
DATEDATE-2002-Scanlon #design
Global Responsibilities in SOC Design (TS), p. 12.
DACDAC-2001-ChoiYLR #embedded #industrial #model checking
Model Checking of S3C2400X Industrial Embedded SOC Product (HC, BWY, YTL, HR), pp. 611–616.
DACDAC-2001-Wingard #integration
MicroNetwork-Based Integration for SOCs (DW), pp. 673–677.
DATEDATE-2001-PiguetRO #power management
Low-power systems on chips (SOCs) (CP, MR, TJFO), p. 488.
DATEDATE-2000-HalambiCGDN #architecture
Architecture Exploration of Parameterizable EPIC SOC Architectures (AH, RC, PG, NDD, AN), p. 748.
DATEDATE-2000-OzevBO #synthesis
Test Synthesis for Mixed-Signal SOC Paths (SO, IB, AO), pp. 128–133.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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