BibSLEIGH — Alex

Travelled to:

4 × USA
6 × France
7 × Germany

Collaborated with:

R.Vemuri Y.Wei C.Ferent H.Tang V.Subramanian M.Gilberti N.Thepayasuwan ∅ F.Jiao S.Montano P.Sun H.Zhang Y.Zhao S.Kallakuri E.A.Feinberg S.Doboli G.Gothoskar A.Núñez-Aldana N.R.Dhanwada S.Ganesan

Talks about:

analog (10) synthesi (8) circuit (8) system (8) design (8) topolog (4) network (4) model (4) reconfigur (3) methodolog (3)

Person: Alex Doboli

DBLP: Doboli:Alex

Contributed to:

2015

2014

2011

2010

2009

2007

2006

2005

2004

2003

2002

2001

1999

Wrote 20 papers:

DATE-2015-JiaoMD #reasoning #synthesis: Knowledge-intensive, causal reasoning for analog circuit topology synthesis in emergent and innovative applications (FJ, SM, AD), pp. 1144–1149.
DATE-2014-FerentD #comparison #mining #novel #synthesis #using: Novel circuit topology synthesis method using circuit feature mining and symbolic comparison (CF, AD), pp. 1–4.
DATE-2011-FerentD #automation #design #similarity: A symbolic technique for automated characterization of the uniqueness and similarity of analog circuit design features (CF, AD), pp. 1212–1217.
DATE-2010-FerentSGD #approach #embedded #linear #network #programming: Linear programming approach for performance-driven data aggregation in networks of embedded sensors (CF, VS, MG, AD), pp. 1456–1461.
DATE-2009-SubramanianGD #adaptation #configuration management #design #embedded #grid #network #online #policy: Online adaptation policy design for grid sensor networks with reconfigurable embedded nodes (VS, MG, AD), pp. 1273–1278.
DATE-2007-SunWD #configuration management #design: Flexibility-oriented design methodology for reconfigurable DeltaSigma modulators (PS, YW, AD), pp. 415–420.
DAC-2006-WeiD #composition #development #megamodelling: Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decoupling (YW, AD), pp. 1023–1028.
DATE-2006-WeiTD #communication #configuration management #design #multi: Systematic methodology for designing reconfigurable Delta-Sigma modulator topologies for multimode communication systems (YW, HT, AD), pp. 393–398.
DATE-2006-ZhangZD #modelling #named #parametricity #process: ALAMO: an improved alpha-space based methodology for modeling process parameter variations in analog circuits (HZ, YZ, AD), pp. 156–161.
DAC-2005-WeiD #behaviour #development #megamodelling: Systematic development of analog circuit structural macromodels through behavioral model decoupling (YW, AD), pp. 57–62.
DATE-2005-KallakuriDF #communication: Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip (SK, AD, EAF), pp. 826–827.
DATE-2005-TangWD #complexity #power management #synthesis: MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption (HT, YW, AD), pp. 264–269.
DATE-v1-2004-ThepayasuwanD #architecture #layout #synthesis: Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip (NT, AD), pp. 108–113.
DATE-2003-DoboliGD #clustering #modelling #network #using: Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering (SD, GG, AD), pp. 11098–11099.
DATE-2002-DoboliV #co-evolution #design #functional #specification: A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems (AD, RV), pp. 760–767.
DAC-2001-DoboliV #constraints #design #synthesis: Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints (AD, RV), pp. 629–634.
DATE-2001-Doboli #constraints #design #embedded #latency: Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraints (AD), pp. 612–619.
DATE-2001-DoboliV #analysis #network #scalability: A regularity-based hierarchical symbolic analysis method for large-scale analog networks (AD, RV), p. 806.
DAC-1999-DoboliNDGV #behaviour #design #synthesis #using: Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration (AD, ANA, NRD, SG, RV), pp. 951–957.
DATE-1999-DoboliV #architecture #behaviour #compilation #generative #synthesis: A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems (AD, RV), pp. 338–345.