BibSLEIGH — Alberto

Travelled to:

4 × USA
6 × France
6 × Germany

Collaborated with:

E.Macii M.Poncino L.Benini R.Scarsi A.Calimera A.V.Sathanur G.Castelli S.Rinaudo P.Babighian A.Ivaldi F.Crudo R.Zafalon D.Bruni G.Gangemi L.M.V.Bolzani L.Macchiarulo A.Pullini A.Chakraborty P.Sithambaram K.Duraisami E.Omerbegovic F.Pro G.D.Micheli A.Sassone R.Goldman V.Melikyan E.Babayan

Talks about:

power (8) system (5) design (5) memori (4) energi (4) effici (4) embed (4) synthesi (3) enabl (3) clock (3)

Person: Alberto Macii

DBLP: Macii:Alberto

Contributed to:

2012

2011

2009

2008

2007

2006

2004

2003

2002

2001

2000

1999

Wrote 18 papers:

DATE-2012-SassoneCMMPGMBR #dependence #network: Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks (AS, AC, AM, EM, MP, RG, VM, EB, SR), pp. 165–166.
DATE-2011-RinaudoGCMP #approach #design #energy #performance #power management: Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems (SR, GG, AC, AM, MP), pp. 1127–1128.
DATE-2009-BolzaniCMMP #concurrent #design #industrial #power management: Enabling concurrent clock and power gating in an industrial design flow (LMVB, AC, AM, EM, MP), pp. 334–339.
DATE-2008-SathanurPBMMP #algorithm #framework #scalability: A Scalable Algorithmic Framework for Row-Based Power-Gating (AVS, AP, LB, AM, EM, MP), pp. 379–384.
DATE-2007-SathanurCBMMP #bound #clustering #interactive #performance: Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing (AVS, AC, LB, AM, EM, MP), pp. 1544–1549.
DATE-2006-BabighianBMM: Enabling fine-grain leakage management by voltage anchor insertion (PB, LB, AM, EM), pp. 868–873.
DATE-2006-ChakrabortySDMMP #bound #optimisation: Thermal resilient bounded-skew clock tree optimization methodology (AC, PS, KD, AM, EM, MP), pp. 832–837.
DATE-v1-2004-BeniniIMM #design #memory management #metaprogramming: Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning (LB, AI, AM, EM), pp. 698–699.
DAC-2003-BeniniMMOPP #analysis #design #difference #energy: Energy-aware design techniques for differential power analysis protection (LB, AM, EM, EO, FP, MP), pp. 36–41.
DATE-2003-MaciiMCZ #algorithm #embedded #energy: A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors (AM, EM, FC, RZ), pp. 10024–10029.
DATE-2003-MaciiMP #clustering #memory management #performance: Improving the Efficiency of Memory Partitioning by Address Clustering (AM, EM, MP), pp. 10018–10023.
DATE-2002-BeniniBMM #embedded #energy: Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors (LB, DB, AM, EM), pp. 449–453.
DAC-2001-BeniniMMMP #architecture #embedded #layout #memory management #synthesis: From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip (LB, LM, AM, EM, MP), pp. 784–789.
DATE-2001-BeniniCMMPS #scheduling: Extending lifetime of portable systems by battery scheduling (LB, GC, AM, EM, MP, RS), pp. 197–203.
DAC-2000-BeniniMMP #embedded #optimisation #synthesis: Synthesis of application-specific memories for power optimization in embedded systems (LB, AM, EM, MP), pp. 300–303.
DATE-2000-BeniniCMMPS #estimation: A Discrete-Time Battery Model for High-Level Power Estimation (LB, GC, AM, EM, MP, RS), pp. 35–39.
DAC-1999-BeniniMMPS #communication #interface #power management #synthesis: Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses (LB, AM, EM, MP, RS), pp. 128–133.
DATE-1999-BeniniMMMPS #power management: Glitch Power Minimization by Gate Freezing (LB, GDM, AM, EM, MP, RS), pp. 163–167.