BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
3 × Germany
4 × USA
5 × France
Collaborated with:
C.Huang C.Chen J.Li H.Shih J.Lu Y.Li S.Wang H.Chang J.Huang D.Kwai K.(.Cheng C.Wu K.Cheng C.Wang C.Wang S.Huang C.Lo M.Lee J.Yeh H.Huang J.Chen C.Su C.Cheng S.Chen C.Hwang H.Lin C.Li C.Lee S.Chang L.Denq C.Chi H.Hsu M.Chu J.Liou P.Huang H.Ma J.Bor C.Tien C.Wang Y.Kuo T.Chang
Talks about:
test (5) scheme (4) memori (4) design (4) toler (2) simul (2) logic (2) fault (2) port (2) cost (2)

Person: Cheng-Wen Wu

DBLP DBLP: Wu:Cheng=Wen

Contributed to:

DATE 20132013
DAC 20112011
DAC 20102010
DATE 20102010
DAC 20062006
DATE 20052005
DATE 20022002
DAC 20012001
DATE 20012001
DATE 20002000
ED&TC 19971997

Wrote 13 papers:

DATE-2013-ShihW #3d #fault
An enhanced double-TSV scheme for defect tolerance in 3D-IC (HCS, CWW), pp. 1486–1489.
DAC-2011-LiLWCDCHCLHHMBWTWKHC #interface #low cost #testing
A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing (CFL, CYL, CHW, SLC, LMD, CCC, HJH, MYC, JJL, SYH, PCH, HPM, JCB, CWW, CCT, CHW, YSK, CTH, TYC), pp. 771–776.
DAC-2010-ChangHKCW #3d #fault
An error tolerance scheme for 3D CMOS imagers (HMC, JLH, DMK, KT(C, CWW), pp. 917–922.
DAC-2010-WangCW #identification #performance
Fast identification of operating current for toggle MRAM by spiral search (SHW, CYC, CWW), pp. 923–928.
DATE-2010-ChenW #adaptation #memory management #random
An adaptive code rate EDAC scheme for random access memory (CYC, CWW), pp. 735–740.
DAC-2006-WangLLYHWH #design #framework #network #platform #security
A network security processor design based on an integrated SOC design and test platform (CHW, CYL, MSL, JCY, CTH, CWW, SYH), pp. 490–495.
DATE-2005-Wu #testing
SOC Testing Methodology and Practice (CWW), pp. 1120–1121.
DATE-2002-LiHCSWCCHL #design
A Hierarchical Test Scheme for System-On-Chip Designs (JFL, HJH, JBC, CPS, CWW, CC, SIC, CYH, HPL), pp. 486–490.
DAC-2001-WuHCWW #algorithm #generative #multi #scheduling
Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories (CFW, CTH, KLC, CWW, CWW), pp. 301–306.
DATE-2001-LiW #fault #memory management
Memory fault diagnosis by syndrome compression (JFL, CWW), pp. 97–101.
DATE-2000-LuW #logic #memory management #modelling
Cost and Benefit Models for Logic and Memory BIST (JML, CWW), pp. 710–714.
EDTC-1997-HuangW #array #design #performance
High-speed C-testable systolic array design for Galois-field inversion (CTH, CWW), pp. 342–346.
EDAC-1994-LiW #automaton #fault #logic #simulation
Logic and Fault Simulation by Cellular Automata (YLL, CWW), pp. 552–556.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.