BibSLEIGH — Yosinori

Travelled to:

3 × USA
4 × Germany
5 × France

Collaborated with:

A.Kondratyev L.Lavagno C.Passerone M.Meyer R.K.Brayton X.Chen H.Hsieh M.Marek-Sadowska F.Balarin Y.Ran A.L.Sangiovanni-Vincentelli V.Shah B.Hu A.G.Lomeña M.L.López-Vallejo D.Jongeneel R.H.J.M.Otten A.Davare G.Arrigoni L.Duchini D.Chai K.H.Tseng J.Cortadella M.Massot S.Moral

Talks about:

schedul (5) level (5) analysi (4) base (4) synthesi (3) generat (3) high (3) constraint (2) technolog (2) crosstalk (2)

Person: Yosinori Watanabe

DBLP: Watanabe:Yosinori

Contributed to:

2013

2012

2011

2005

2004

2003

2002

2001

2000

1994

Wrote 16 papers:

DATE-2013-KondratyevLMW #evaluation #synthesis: Share with care: a quantitative evaluation of sharing approaches in high-level synthesis (AK, LL, MM, YW), pp. 1547–1552.
DATE-2012-KondratyevLMW #synthesis #trade-off: Exploiting area/delay tradeoffs in high-level synthesis (AK, LL, MM, YW), pp. 1024–1029.
DATE-2011-KondratyevLMW #pipes and filters #synthesis: Realistic performance-constrained pipelining in high-level synthesis (AK, LL, MM, YW), pp. 1382–1387.
DAC-2005-ChenDHSW #analysis #concurrent #design #simulation: Simulation based deadlock analysis for system level designs (XC, AD, HH, ALSV, YW), pp. 260–265.
DATE-2005-LavagnoPSW #design #slicing: A Time Slice Based Scheduler Model for System Level Design (LL, CP, VS, YW), pp. 378–383.
DATE-v2-2004-RanKWM #analysis: Eliminating False Positives in Crosstalk Noise Analysis (YR, AK, YW, MMS), pp. 1192–1197.
DAC-2003-ChaiKRTWM #analysis: Temporofunctional crosstalk noise analysis (DC, AK, YR, KHT, YW, MMS), pp. 860–863.
DAC-2003-ChenHBW #analysis #automation #constraints #logic: Automatic trace analysis for logic of constraints (XC, HH, FB, YW), pp. 460–465.
DAC-2003-HuWKM #library: Gain-based technology mapping for discrete-size cell libraries (BH, YW, AK, MMS), pp. 574–579.
DATE-2003-ChenHBW #automation #constraints #generative #monitoring #simulation: Automatic Generation of Simulation Monitors from Quantitative Constraint Formula (XC, HH, FB, YW), pp. 11174–11175.
DATE-2003-LomenaLWK #approach #explosion #performance #scheduling: An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling (AGL, MLLV, YW, AK), pp. 10428–10435.
DATE-2002-ArrigoniDPLW #scheduling: False Path Elimination in Quasi-Static Scheduling (GA, LD, CP, LL, YW), pp. 964–970.
DATE-2001-PasseroneWL #generative #graph #scheduling: Generation of minimal size code for scheduling graphs (CP, YW, LL), pp. 668–673.
DAC-2000-CortadellaKLMMPWS #embedded #generative #scheduling: Task generation and compile-time scheduling for mixed data-control embedded software (JC, AK, LL, MM, SM, CP, YW, ALSV), pp. 489–494.
DAC-2000-JongeneelWBO: Area and search space control for technology mapping (DJJ, YW, RKB, RHJMO), pp. 86–91.
EDAC-1994-WatanabeB #automaton #nondeterminism #pseudo: State Minimization of Pseudo Non-Deterministic FSM’s (YW, RKB), pp. 184–191.