BibSLEIGH
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
EDIT!
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
4 × France
4 × Germany
Collaborated with:
F.V.Fernández F.Medeiro M.Yavari O.Shoaei R.Castro-López O.Guerra E.Roca R.Domínguez-Castro J.L.d.l.Rosa R.d.Río M.B.Pérez-Verdú M.Delgado-Restituto I.Garcia-Vargas M.Galan R.Carmona-Galán F.Jiménez-Garrido S.Espejo-Meana F.M.Pérez-Montes J.D.Rodríguez-García J.Ruiz-Amaya
Talks about:
sigma (4) modul (4) delta (4) design (3) analog (3) generat (2) circuit (2) analysi (2) symbol (2) singl (2)

Person: Ángel Rodríguez-Vázquez

DBLP DBLP: Rodr=iacute=guez-V=aacute=zquez:=Aacute=ngel

Contributed to:

DATE 20062006
DATE DF 20042004
DATE 20032003
DATE 20022002
DATE 20012001
DATE 20002000
DATE 19991999
ED&TC 19971997

Wrote 11 papers:

DATE-2006-YavariSR #design #hybrid
Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation (MY, OS, ÁRV), pp. 144–149.
DATE-2006-YavariSR06a
Double-sampling single-loop sigma-delta modulator topologies for broadband applications (MY, OS, ÁRV), pp. 399–404.
DATE-DF-2004-Ruiz-AmayaRMFRPR #matlab #synthesis
MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time [Sigma, Delta] Modulators (JRA, JLdlR, FM, FVF, RdR, MBPV, ÁRV), pp. 150–155.
DATE-2003-Castro-LopezFMR #behaviour #hardware #modelling #simulation #using
Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages (RCL, FVF, FM, ÁRV), pp. 10168–10175.
DATE-2002-CarmonaJDER #design #programmable
Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip (RCG, FJG, RDC, SEM, ÁRV), pp. 362–366.
DATE-2001-Castro-LopezFDR
Retargeting of mixed-signal blocks for SoCs (RCL, FVF, MDR, ÁRV), pp. 772–775.
DATE-2001-RioRMPR #design #top-down
Top-down design of a xDSL 14-bit 4MS/s sigma-delta modulator in digital CMOS technology (RdR, JLdlR, FM, MBPV, ÁRV), pp. 348–352.
DATE-2000-GuerraRFR #analysis #approach #scalability
A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits (OG, ER, FVF, ÁRV), pp. 48–52.
DATE-2000-Perez-MontesMDFR #named
XFridge: A SPICE-Based, Portable, User-Friendly Cell-Level Sizing Tool (FMPM, FM, RDC, FVF, ÁRV), p. 739.
DATE-1999-GuerraRRFR #fault #generative
An Accurate Error Control Mechanism for Simplification Before Generation Algorihms (OG, JDRG, ER, FVF, ÁRV), p. 412–?.
EDTC-1997-Garcia-VargasGFR #algorithm #analysis #generative #scalability
An algorithm for numerical reference generation in symbolic analysis of large analog circuits (IGV, MG, FVF, ÁRV), pp. 395–399.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.