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Travelled to:
1 × France
3 × USA
Collaborated with:
D.Sylvester D.Blaauw S.Shah K.Agarwal S.W.Director R.Puri L.Stok J.M.Cohn D.S.Kung D.Z.Pan S.H.Kulkarni
Talks about:
power (5) size (3) dual (3) vth (3) perform (2) variat (2) leakag (2) consid (2) assign (2) gate (2)

Person: Ashish Srivastava

DBLP DBLP: Srivastava:Ashish

Contributed to:

DAC 20052005
DAC 20042004
DATE v1 20042004
DAC 20032003

Wrote 5 papers:

DAC-2005-SrivastavaSASBD #correlation #estimation #parametricity #performance #power management
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance (AS, SS, KA, DS, DB, SWD), pp. 535–540.
DAC-2004-SrivastavaSB #optimisation #power management #process #statistics #using
Statistical optimization of leakage power considering process variations using dual-Vth and sizing (AS, DS, DB), pp. 773–778.
DAC-2004-SrivastavaSB04a #power management #using
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment (AS, DS, DB), pp. 783–787.
DATE-v1-2004-SrivastavaSB #concurrent #design #power management
Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design (AS, DS, DB), pp. 718–719.
DAC-2003-PuriSCKPSSK #performance
Pushing ASIC performance in a power envelope (RP, LS, JMC, DSK, DZP, DS, AS, SHK), pp. 788–793.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.