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Travelled to:
5 × USA
Collaborated with:
C.W.Gwyn W.L.Buntine D.D.Hill P.G.Karger W.M.v.Cleemput J.Cong C.L.Liu M.Pedram D.Curry
Talks about:
automat (4) cell (4) layout (3) design (3) mask (3) placement (2) benchmark (2) algorithm (2) silicon (2) circuit (2)

Person: Bryan Preas

DBLP DBLP: Preas:Bryan

Facilitated 1 volumes:

DAC 1995Ed

Contributed to:

DAC 19901990
DAC 19891989
DAC 19871987
DAC 19861986
DAC 19791979
DAC 19781978
DAC 19761976

Wrote 9 papers:

DAC-1990-CongPL #algorithm #design #modelling #standard
General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design (JC, BP, CLL), pp. 709–715.
DAC-1990-HillP #benchmark #metric #synthesis
Benchmarks for Cell Synthesis (DDH, BP), pp. 317–320.
DAC-1989-PreasPC #automation #hybrid #layout
Automatic Layout of Silicon-on-Silicon Hybrid Packages (BP, MP, DC), pp. 394–399.
DAC-1987-Preas #benchmark #layout #metric
Benchmarks for Cell-Based Layout Systems (BP), pp. 319–320.
DAC-1986-PreasK #automation #overview
Automatic placement a review of current techniques (BP, PGK), pp. 622–629.
DAC-1979-PreasC #algorithm
Placement algorithms for arbitrarily shaped blocks (BP, WMvC), pp. 474–480.
DAC-1978-PreasG #automation #layout
Methods for hierarchical automatic layout of custom LSI circuit masks (BP, CWG), pp. 206–212.
DAC-1976-BuntineP #analysis #design
Design rule checking and analysis of IC mask designs (WLB, BP), pp. 301–308.
DAC-1976-PreasBG #analysis #automation
Automatic circuit analysis based on mask information (BP, WLB, CWG), pp. 309–317.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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