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Travelled to:
1 × Brazil
1 × USA
2 × Germany
3 × France
Collaborated with:
R.Weiß N.Druml A.Genser J.Haid U.Neffe A.Mühlberger J.Lauber M.Karner E.Armengaud G.Grießnig R.Mader A.Höller C.Kreiner T.Felicijan C.Bachmann J.Hulzink M.Berekovic Sarah Haas Andreas Wallner Ronald Toegl Thomas Ulz M.Wendt M.Grumer V.Derbek D.Wischounig J.Preishuber-Pfluegl M.Pistauer K.Rothbart E.Rieger M.Menghin H.Bock
Talks about:
power (6) base (5) system (3) smart (3) card (3) voltag (2) suppli (2) design (2) simul (2) model (2)

Person: Christian Steger

DBLP DBLP: Steger:Christian

Contributed to:

DAC 20142014
PDP 20132013
DATE 20122012
DATE 20102010
DATE 20092009
SAC 20082008
DATE 20072007
DATE DF 20042004
SAC 19991999
CASE 20172017

Wrote 11 papers:

DAC-2014-HollerDKSF #co-evolution #design #encryption #hardware
Hardware/Software Co-Design of Elliptic-Curve Cryptography for Resource-Constrained Applications (AH, ND, CK, CS, TF), p. 6.
PDP-2013-DrumlMSWGBH #behaviour #design #functional #performance #verification
Emulation-Based Test and Verification of a Design’s Functional, Performance, Power, and Supply Voltage Behavior (ND, MM, CS, RW, AG, HB, JH), pp. 328–335.
DATE-2012-DrumlSWGH #estimation #manycore #smarttech
Estimation based power and supply voltage management for future RF-powered multi-core smart cards (ND, CS, RW, AG, JH), pp. 358–363.
DATE-2010-KarnerASW #network #runtime #simulation #using
Holistic simulation of FlexRay networks by using run-time model switching (MK, EA, CS, RW), pp. 544–549.
DATE-2009-BachmannGHBS #power management
A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing (CB, AG, JH, MB, CS), pp. 1614–1619.
DATE-2009-GriessnigMSW #fault #novel #testing
Fault insertion testing of a novel CPLD-based fail-safe system (GG, RM, CS, RW), pp. 214–219.
SAC-2008-WendtGSWNM #analysis #mobile #optimisation #smarttech
System level power profile analysis and optimization for smart cards and mobile devices (MW, MG, CS, RW, UN, AM), pp. 1884–1888.
DATE-2007-DerbekSWWPP #framework #platform #simulation
Simulation platform for UHF RFID (VD, CS, RW, DW, JPP, MP), pp. 918–923.
DATE-DF-2004-NeffeRSWRM #energy #estimation #modelling #power management #smarttech
Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards (UN, KR, CS, RW, ER, AM), pp. 300–305.
SAC-1999-LauberSW #assurance #online #probability #quality #safety
Applied Probabilistic AI for Online Diagnosis of a Safety-Critical System Based on a Quality Assurance Program (JL, CS, RW), pp. 25–30.
CASE-2017-HaasWTUS #approach #authentication #industrial #mobile
A secured offline authentication approach for industrial mobile robots (SH, AW, RT, TU, CS), pp. 308–313.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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