Travelled to:1 × Germany
1 × USA
2 × France
Collaborated with:P.Siegl R.Buchty H.Al-Khalissi S.A.A.Shah P.Pirsch C.Bachmann A.Genser J.Hulzink C.Steger C.Arbelo A.Kanstein S.López J.F.López R.Sarmiento J.Mignolet J.P.Wittenburg W.Hinrichs J.Kneip M.Ohmacht H.Lieske H.Kloos H.Stolberg L.Friebe S.Moch S.Flügel X.Mao M.B.Kulaczewski H.Klußmann
Talks about:process (3) applic (3) architectur (2) parallel (2) perform (2) intens (2) reconfigur (1) multimedia (1) implement (1) wideband (1)
Person: Mladen Berekovic
DBLP: Berekovic:Mladen
Contributed to:
20152014
200920072003
1998Wrote 6 papers:
- PDP-2015-SieglBB #hybrid #performance
- Revealing Potential Performance Improvements by Utilizing Hybrid Work-Sharing for Resource-Intensive Seismic Applications (PS, RB, MB), pp. 659–663.
- PDP-2014-Al-KhalissiSB #implementation #parallel #performance
- An Efficient Barrier Implementation for OpenMP-Like Parallelism on the Intel SCC (HAK, SAAS, MB), pp. 76–83.
- DATE-2009-BachmannGHBS #power management
- A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing (CB, AG, JH, MB, CS), pp. 1614–1619.
- DATE-2007-ArbeloKLLBSM #architecture #configuration management #kernel #video
- Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter (CA, AK, SL, JFL, MB, RS, JYM), pp. 177–182.
- DATE-2003-StolbergBFMFMKKP #architecture #manycore #named
- HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications (HJS, MB, LF, SM, SF, XM, MBK, HK, PP), pp. 20008–20013.
- DAC-1998-WittenburgHKOBLKP #image #parallel #performance #programmable
- Realization of a Programmable Parallel DSP for High Performance Image Processing Applications (JPW, WH, JK, MO, MB, HL, HK, PP), pp. 56–61.