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Travelled to:
1 × Brazil
1 × Switzerland
3 × France
3 × Germany
Collaborated with:
C.Steger B.Rinner N.Druml A.Genser J.Haid A.Leitner C.Kreiner U.Neffe A.Mühlberger M.Schmid J.Lauber M.Platzner M.Karner E.Armengaud G.Grießnig R.Mader M.Wendt M.Grumer V.Derbek D.Wischounig J.Preishuber-Pfluegl M.Pistauer K.Rothbart E.Rieger M.Menghin H.Bock
Talks about:
base (6) power (5) system (4) multi (4) smart (3) simul (3) model (3) card (3) architectur (2) voltag (2)

Person: Reinhold Weiß

DBLP DBLP: Wei=szlig=:Reinhold

Contributed to:

PDP 20132013
DATE 20122012
PLEASE 20122012
DATE 20102010
DATE 20092009
SAC 20082008
DATE 20072007
DATE DF 20042004
DATE 20032003
SAC 19991999
PDP 19951995

Wrote 11 papers:

PDP-2013-DrumlMSWGBH #behaviour #design #functional #performance #verification
Emulation-Based Test and Verification of a Design’s Functional, Performance, Power, and Supply Voltage Behavior (ND, MM, CS, RW, AG, HB, JH), pp. 328–335.
DATE-2012-DrumlSWGH #estimation #manycore #smarttech
Estimation based power and supply voltage management for future RF-powered multi-core smart cards (ND, CS, RW, AG, JH), pp. 358–363.
PLEASE-2012-LeitnerWK #multi #optimisation #problem
Optimizing problem space representations through domain multi-modeling (AL, RW, CK), pp. 49–52.
DATE-2010-KarnerASW #network #runtime #simulation #using
Holistic simulation of FlexRay networks by using run-time model switching (MK, EA, CS, RW), pp. 544–549.
DATE-2009-GriessnigMSW #fault #novel #testing
Fault insertion testing of a novel CPLD-based fail-safe system (GG, RM, CS, RW), pp. 214–219.
SAC-2008-WendtGSWNM #analysis #mobile #optimisation #smarttech
System level power profile analysis and optimization for smart cards and mobile devices (MW, MG, CS, RW, UN, AM), pp. 1884–1888.
DATE-2007-DerbekSWWPP #framework #platform #simulation
Simulation platform for UHF RFID (VD, CS, RW, DW, JPP, MP), pp. 918–923.
DATE-DF-2004-NeffeRSWRM #energy #estimation #modelling #power management #smarttech
Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards (UN, KR, CS, RW, ER, AM), pp. 300–305.
DATE-2003-RinnerSW #agile #architecture #embedded #flexibility #multi #prototype
Rapid Prototyping of Flexible Embedded Systems on Multi-DSP Architectures (BR, MS, RW), pp. 10204–10211.
SAC-1999-LauberSW #assurance #online #probability #quality #safety
Applied Probabilistic AI for Online Diagnosis of a Safety-Critical System Based on a Quality Assurance Program (JL, CS, RW), pp. 25–30.
PDP-1995-PlatznerRW #architecture #distributed #multi #simulation
A distributed computer architecture for qualitative simulation based on a multi-DSP and FPGAs (MP, BR, RW), pp. 311–318.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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