Travelled to:3 × France
5 × USA
Collaborated with:Y.Huang M.Yu ∅ S.Huang T.M.Niermann J.H.Patel M.Tsai K.H.Tsai X.Tang R.Guo S.M.Reddy C.Hsieh H.Tseng A.Huang Y.Hung Y.Lin K.Tsai S.K.Sunter Y.Chou D.Kwai
Talks about:test (4) fault (3) diagnosi (2) generat (2) circuit (2) memori (2) simul (2) delay (2) chain (2) scan (2)
Person: Wu-Tung Cheng
DBLP: Cheng:Wu=Tung
Contributed to:
2015
2012200920042003199019891988Wrote 8 papers:
- DATE-2015-HuangTTC #architecture
- Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects (SYH, MTT, KHHT, WTC), pp. 924–927.
- DAC-2012-HuangLTCSCK #3d #testing
- Small delay testing for TSVs in 3-D ICs (SYH, YHL, KHT, WTC, SKS, YFC, DMK), pp. 1031–1036.
- DATE-2009-TangGCR #generative #multi
- Improving compressed test pattern generation for multiple scan chain failure diagnosis (XT, RG, WTC, SMR), pp. 1000–1005.
- DATE-v2-2004-HuangCHTHH #analysis #fault #probability
- Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis (YH, WTC, CJH, HYT, AH, YTH), pp. 1072–1077.
- DAC-2003-HuangC #embedded #framework #using #verification
- Using embedded infrastructure IP for SOC post-silicon verification (YH, WTC), pp. 674–677.
- DAC-1990-NiermannCP #fault #memory management #named #performance #proving
- Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator (TMN, WTC, JHP), pp. 535–540.
- DAC-1989-ChengY #difference #fault #memory management #performance #simulation #using
- Differential Fault Simulation — a Fast Method Using Minimal Memory (WTC, MLY), pp. 424–428.
- DAC-1988-Cheng #generative #testing
- Split Circuit Model for Test Generation (WTC), pp. 96–101.