Travelled to:1 × France
2 × USA
Collaborated with:K.Cheng M.Marek-Sadowska D.Chang G.Araujo S.Malik Y.Hsu B.Chen M.Fujita C.Lin T.Aikyo
Talks about:test (3) synthesi (2) regist (2) scan (2) path (2) use (2) architectur (1) heterogen (1) transfer (1) overhead (1)
Person: Mike Tien-Chien Lee
DBLP: Lee:Mike_Tien=Chien
Contributed to:
1998
19971996Wrote 5 papers:
- DATE-1998-ChangCML #functional #testing
- Functional Scan Chain Testing (DC, KTC, MMS, MTCL), pp. 278–283.
- DAC-1997-ChangLMAC #approach #synthesis
- A Test Synthesis Approach to Reducing BALLAST DFT Overhead (DC, MTCL, MMS, TA, KTC), pp. 466–471.
- DAC-1996-AraujoML #architecture #code generation #using
- Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures (GA, SM, MTCL), pp. 591–596.
- DAC-1996-LeeHCF #design #modelling #synthesis #using
- Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL (MTCL, YCH, BC, MF), pp. 585–590.
- DAC-1996-LinMCL #logic
- Test Point Insertion: Scan Paths through Combinational Logic (CCL, MMS, KTC, MTCL), pp. 268–273.