Travelled to:2 × USA
3 × Germany
Collaborated with:R.Leupers H.Meyr G.Ascheid W.Sheng M.Hohenauer G.Braun J.Castrillón H.Scharwächter F.Angiolini F.Ferrari C.Ferri L.Benini R.Velasquez A.Stulova A.Nohl T.Isshiki H.Kunieda
Talks about:mpsoc (3) framework (2) integr (2) design (2) applic (2) base (2) map (2) heterogen (1) simultan (1) retarget (1)
Person: Jianjiang Ceng
DBLP: Ceng:Jianjiang
Contributed to:
2010
2008200620052004Wrote 5 papers:
- DATE-2010-CastrillonVSSCLAM #analysis
- Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms (JC, RV, AS, WS, JC, RL, GA, HM), pp. 753–758.
- DAC-2008-CengCSSLAMIK #framework #named #parallel
- MAPS: an integrated framework for MPSoC application parallelization (JC, JC, WS, HS, RL, GA, HM, TI, HK), pp. 754–759.
- DATE-2006-AngioliniCLFFB #design #framework
- An integrated open framework for heterogeneous MPSoC design space exploration (FA, JC, RL, FF, CF, LB), pp. 1145–1150.
- DATE-2005-CengHLAMB #c #compilation #modelling #semantics
- C Compiler Retargeting Based on Instruction Semantics Models (JC, MH, RL, GA, HM, GB), pp. 1150–1155.
- DAC-2004-BraunNSCHSLM #approach #consistency #design #flexibility #novel
- A novel approach for flexible and consistent ADL-driven ASIP design (GB, AN, WS, JC, MH, HS, RL, HM), pp. 717–722.