BibSLEIGH — Heinrich

Travelled to:

11 × USA
6 × France
8 × Germany

Collaborated with:

R.Leupers G.Ascheid A.Hoffmann G.Braun A.Nohl T.Kogel K.Karuri T.Grötker O.Schliebusch S.Pees V.Zivojnovic M.Hohenauer H.Keding S.Kraemer A.Chattopadhyay H.Scharwächter J.Ceng M.Coors J.Horstmannshoff M.Willems D.Kammler W.Sheng A.Lock R.Camposano R.Schoenen P.Zepter T.Kempf A.Wieferink H.Ishebabi O.Wahlen O.Lüthje J.Castrillón E.M.Witte M.Kedia V.Bürsgens L.Gao X.Chen S.Wallentowitz M.A.A.Faruque T.Glökler F.Engel G.Bette B.Singh W.Ahmed M.Doerper B.Vanthournout V.Greive R.Velasquez A.Stulova M.Steinert T.Isshiki H.Kunieda B.Geukes L.Fanucci M.Cassiano S.Saponara H.v.Someren

Talks about:

processor (11) design (9) simul (8) use (8) architectur (6) explor (6) model (6) system (5) compil (5) level (5)

Person: Heinrich Meyr

DBLP: Meyr:Heinrich

Contributed to:

2010

2008

2007

2006

2005

2004

2003

2002

2001

2000

1999

1998

1997

1996

1995

Wrote 36 papers:

DATE-2010-CastrillonVSSCLAM #analysis: Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms (JC, RV, AS, WS, JC, RL, GA, HM), pp. 753–758.
DAC-2008-CengCSSLAMIK #framework #named #parallel: MAPS: an integrated framework for MPSoC application parallelization (JC, JC, WS, HS, RL, GA, HM, TI, HK), pp. 754–759.
DAC-2008-GaoKKLAM #estimation #hybrid #multi #performance #simulation #using: Multiprocessor performance estimation using hybrid simulation (LG, KK, SK, RL, GA, HM), pp. 325–330.
DATE-2008-ChattopadhyayCILAM #architecture #configuration management #modelling: High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures (AC, XC, HI, RL, GA, HM), pp. 1334–1339.
DATE-2008-HohenauerELAMBS #execution #optimisation: Retargetable Code Optimization for Predicated Execution (MH, FE, RL, GA, HM, GB, BS), pp. 1492–1497.
DATE-2007-ChattopadhyayAKKLAM #configuration management #design #embedded: Design space exploration of partially re-configurable embedded processors (AC, WA, KK, DK, RL, GA, HM), pp. 319–324.
DATE-2007-KraemerLAM #interactive #parallel #program transformation #source code #using: Interactive presentation: SoftSIMD — exploiting subword parallelism using source code transformations (SK, RL, GA, HM), pp. 1349–1354.
DATE-2006-ChattopadhyayGKWSILAM #automation #embedded: Automatic ADL-based operand isolation for embedded processors (AC, BG, DK, EMW, OS, HI, RL, GA, HM), pp. 600–605.
DATE-2006-KempfKWALM #estimation #fine-grained #framework #performance #using: A SW performance estimation framework for early system-level-design using fine-grained instrumentation (TK, KK, SW, GA, RL, HM), pp. 468–473.
DATE-2006-ScharwachterHLAM #hardware #interprocedural #multi #network #optimisation #thread #using: An interprocedural code optimization technique for network processors using hardware multi-threading support (HS, MH, RL, GA, HM), pp. 919–924.
DATE-DF-2006-FanucciCSKWSALM #design #image #linear #synthesis: ASIP design and synthesis for non linear filtering in image processing (LF, MC, SS, DK, EMW, OS, GA, RL, HM), pp. 233–238.
DATE-DF-2006-KaruriLAMK #composition #design #float #implementation: Design and implementation of a modular and portable IEEE 754 compliant floating-point unit (KK, RL, GA, HM, MK), pp. 221–226.
DAC-2005-KaruriFKLAM #design #fine-grained #profiling #source code: Fine-grained application source code profiling for ASIP design (KK, MAAF, SK, RL, GA, HM), pp. 329–334.
DATE-2005-CengHLAMB #c #compilation #modelling #semantics: C Compiler Retargeting Based on Instruction Semantics Models (JC, MH, RL, GA, HM, GB), pp. 1150–1155.
DATE-2005-KempfDLAMKV #composition #framework #multi #simulation: A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms (TK, MD, RL, GA, HM, TK, BV), pp. 876–881.
DAC-2004-BraunNSCHSLM #approach #consistency #design #flexibility #novel: A novel approach for flexible and consistent ADL-driven ASIP design (GB, AN, WS, JC, MH, HS, RL, HM), pp. 717–722.
DAC-2004-KogelM #energy: Heterogeneous MP-SoC: the solution to energy-efficient signal processing (TK, HM), pp. 686–691.
DATE-DF-2004-SchliebuschCLAMSBN #architecture #implementation #synthesis: RTL Processor Synthesis for Architecture Exploration and Implementation (OS, AC, RL, GA, HM, MS, GB, AN), pp. 156–160.
DATE-v2-2004-HohenauerSKWKLAMBS #c #compilation #generative #modelling: A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models (MH, HS, KK, OW, TK, RL, GA, HM, GB, HvS), pp. 1276–1283.
DATE-v2-2004-WieferinkKLAMBN #communication #framework #multi: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform (AW, TK, RL, GA, HM, GB, AN), pp. 1256–1263.
DAC-2003-NohlGBALSM #architecture #encoding #modelling #synthesis #using: Instruction encoding synthesis for architecture exploration using hierarchical processor models (AN, VG, GB, AH, RL, OS, HM), pp. 262–267.
DATE-2003-BraunWSLMN #abstraction #memory management #multi: Processor/Memory Co-Exploration on Multiple Abstraction Levels (GB, AW, OS, RL, HM, AN), pp. 10966–10973.
DAC-2002-NohlBSLMH #architecture #flexibility #performance #simulation: A universal technique for fast and flexible instruction-set architecture simulation (AN, GB, OS, RL, HM, AH), pp. 22–27.
LCTES-SCOPES-2002-WahlenGNHLM #architecture #case study #compilation: Application specific compiler/architecture codesign: a case study (OW, TG, AN, AH, RL, HM), pp. 185–193.
DAC-2001-KedingCLM #performance #simulation: Fast Bit-True Simulation (HK, MC, OL, HM), pp. 708–713.
DATE-2001-HoffmanKM #framework #performance: A framework for fast hardware-software co-simulation (AH, TK, HM), pp. 760–765.
DATE-2001-HoffmannNPBM #development #generative #quality #tool support #using: Generating production quality software development tools using a machine description language (AH, AN, SP, GB, HM), pp. 674–678.
DATE-2001-LockCM #framework #platform #programmable #question: The programmable platform: does one size fit all? (AL, RC, HM), pp. 226–227.
DAC-2000-HorstmannshoffM #code generation #data flow #graph #performance: Efficient building block based RTL code generation from synchronous data flow graphs (JH, HM), pp. 552–555.
DATE-2000-PeesHM #using: Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language (SP, AH, HM), pp. 669–673.
DAC-1999-PeesHZM #architecture #modelling #named #programmable: LISA — Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures (SP, AH, VZ, HM), pp. 933–938.
DATE-1998-KedingWCM #design #fixpoint #named #simulation: FRIDGE: A Fixed-Point Design and Simulation Environment (HK, MW, MC, HM), pp. 429–435.
DAC-1997-WillemsBKGM #approach #design #fixpoint: System Level Fixed-Point Design Based on an Interpolative Approach (MW, VB, HK, TG, HM), pp. 293–298.
EDTC-1997-GrotkerSM #data flow #modelling #named: PCC: a modeling technique for mixed control/data flow systems (TG, RS, HM), pp. 482–486.
DAC-1996-ZivojnovicM: Compiled HW/SW Co-Simulation (VZ, HM), pp. 690–695.
DAC-1995-ZepterGM #data flow #design #generative #graph #using: Digital Receiver Design Using VHDL Generation from Data Flow Graphs (PZ, TG, HM), pp. 228–233.