BibSLEIGH — Achim

Travelled to:

3 × France
3 × Germany
5 × USA

Collaborated with:

H.Meyr R.Leupers G.Braun A.Hoffmann O.Schliebusch A.Wieferink G.Ascheid E.Haritan S.Pees A.Vajda M.Bekooij S.Ha R.Dömer O.Wahlen T.Glökler T.Kogel V.Greive T.Hattori H.Yagi P.G.Paulin W.Wolf D.Wingard M.Müller W.Sheng J.Ceng M.Hohenauer H.Scharwächter A.Chattopadhyay M.Steinert T.Borgstrom R.Wilson D.Abada A.Dauman R.Chandra O.Mielo C.Cruse

Talks about:

processor (5) architectur (4) explor (4) system (3) synthesi (2) platform (2) instruct (2) flexibl (2) design (2) level (2)

Person: Achim Nohl

DBLP: Nohl:Achim

Contributed to:

2009

2008

2004

2003

2002

2001

Wrote 11 papers:

DAC-2009-BorgstromHWADCMCN #hardware #hybrid #prototype #question: System prototypes: virtual, hardware or hybrid? (TB, EH, RW, DA, AD, RC, OM, CC, AN), pp. 1–3.
DATE-2009-LeupersVBHDN #exclamation #programming: Programming MPSoC platforms: Road works ahead! (RL, AV, MB, SH, RD, AN), pp. 1584–1589.
DAC-2008-HaritanHYPWNWM #challenge #design #exclamation #manycore #question #what: Multicore design is the challenge! what is the solution? (EH, TH, HY, PGP, WW, AN, DW, MM), pp. 128–130.
DAC-2004-BraunNSCHSLM #approach #consistency #design #flexibility #novel: A novel approach for flexible and consistent ADL-driven ASIP design (GB, AN, WS, JC, MH, HS, RL, HM), pp. 717–722.
DATE-DF-2004-SchliebuschCLAMSBN #architecture #implementation #synthesis: RTL Processor Synthesis for Architecture Exploration and Implementation (OS, AC, RL, GA, HM, MS, GB, AN), pp. 156–160.
DATE-v2-2004-WieferinkKLAMBN #communication #framework #multi: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform (AW, TK, RL, GA, HM, GB, AN), pp. 1256–1263.
DAC-2003-NohlGBALSM #architecture #encoding #modelling #synthesis #using: Instruction encoding synthesis for architecture exploration using hierarchical processor models (AN, VG, GB, AH, RL, OS, HM), pp. 262–267.
DATE-2003-BraunWSLMN #abstraction #memory management #multi: Processor/Memory Co-Exploration on Multiple Abstraction Levels (GB, AW, OS, RL, HM, AN), pp. 10966–10973.
DAC-2002-NohlBSLMH #architecture #flexibility #performance #simulation: A universal technique for fast and flexible instruction-set architecture simulation (AN, GB, OS, RL, HM, AH), pp. 22–27.
LCTES-SCOPES-2002-WahlenGNHLM #architecture #case study #compilation: Application specific compiler/architecture codesign: a case study (OW, TG, AN, AH, RL, HM), pp. 185–193.
DATE-2001-HoffmannNPBM #development #generative #quality #tool support #using: Generating production quality software development tools using a machine description language (AH, AN, SP, GB, HM), pp. 674–678.