Travelled to:1 × Austria
1 × France
6 × USA
Collaborated with:K.Tu V.Balabanov ∅ H.Wang F.Yu T.Hsu C.Chuang Y.Lai M.Widl C.Lai K.Wang T.Chiang K.Chang Y.Liu C.Liu H.K.Chiang Y.Chang S.Chen T.Tsai C.Lin
Talks about:qbf (3) synthesi (2) function (2) resolut (2) circuit (2) analysi (2) string (2) proof (2) minim (2) learn (2)
Person: Jie-Hong R. Jiang
DBLP: Jiang:Jie=Hong_R=
Contributed to:
2015
2015201420142013
201120102009
20182016Wrote 11 papers:
- DAC-2015-ChiangCLJ #design #power management #scalability
- Scalable sequence-constrained retention register minimization in power gating design (TWC, KHC, YTL, JHRJ), p. 6.
- SAT-2015-TuHJ #learning #named #reasoning #satisfiability
- QELL: QBF Reasoning with Extended Clause Learning and Levelized SAT Solving (KHT, TCH, JHRJ), pp. 343–359.
- DAC-2014-ChuangLJ #hybrid #synthesis
- Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits (CCC, YHL, JHRJ), p. 6.
- DAC-2014-LiuCCJ
- Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification (CYL, HJKC, YWC, JHRJ), p. 6.
- SAT-2014-BalabanovWJ #proving
- QBF Resolution Systems and Their Proof Complexities (VB, MW, JHRJ), pp. 154–169.
- DAC-2013-TuJ #feedback #synthesis
- Synthesis of feedback decoders for initialized encoders (KHT, JHRJ), p. 6.
- CAV-2011-BalabanovJ #evaluation #proving
- Resolution Proofs and Skolem Functions in QBF Evaluation and Applications (VB, JHRJ), pp. 149–164.
- DAC-2010-LaiJW #abstraction #learning #named
- BooM: a decision procedure for boolean matching with abstraction and dynamic learning (CFL, JHRJ, KHW), pp. 499–504.
- CAV-2009-Jiang #composition #functional #quantifier
- Quantifier Elimination via Functional Composition (JHRJ), pp. 383–397.
- ASE-2018-WangCYJ #analysis #approach #constraints #model checking #string
- A symbolic model checking approach to the analysis of string and length constraints (HEW, SYC, FY, JHRJ), pp. 623–633.
- CAV-2016-WangTLYJ #analysis #automaton #logic #representation #string
- String Analysis via Automata Manipulation with Logic Circuit Representation (HEW, TLT, CHL, FY, JHRJ), pp. 241–260.