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Travelled to:
2 × France
2 × Germany
3 × USA
Collaborated with:
H.Chou S.Kuo I.L.Markov C.Browy V.Bertacco T.Chiang Y.Liu J.R.Jiang C.Chung C.Chang H.Yu D.Dobbyn
Talks about:
regist (3) design (3) level (3) scalabl (2) analysi (2) improv (2) reset (2) gate (2) care (2) rtl (2)

Person: Kai-Hui Chang

DBLP DBLP: Chang:Kai=Hui

Contributed to:

DAC 20152015
DAC 20122012
DATE 20122012
DATE 20112011
DATE 20102010
DAC 20092009
DATE 20092009

Wrote 7 papers:

DAC-2015-ChiangCLJ #design #power management #scalability
Scalable sequence-constrained retention register minimization in power gating design (TWC, KHC, YTL, JHRJ), p. 6.
DAC-2012-ChangB #simulation
Improving gate-level simulation accuracy when unknowns exist (KHC, CB), pp. 936–940.
DATE-2012-ChangCM #analysis
RTL analysis and modifications for improving at-speed test (KHC, HZC, ILM), pp. 400–405.
Formal reset recovery slack calculation at the register transfer level (CNC, CWC, KHC, SYK), pp. 571–574.
DATE-2010-ChouYCDK #case study #design #nondeterminism #scalability
Finding reset nondeterminism in RTL designs — scalable X-analysis methodology and case study (HZC, HY, KHC, DD, SYK), pp. 1494–1499.
DAC-2009-ChouCK #synthesis
Handling don’t-care conditions in high-level synthesis and application for reducing initialized registers (HZC, KHC, SYK), pp. 412–415.
DATE-2009-ChangBM #design #using
Customizing IP cores for system-on-chip designs using extensive external don’t-cares (KHC, VB, ILM), pp. 582–585.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.