Travelled to:1 × Ireland
1 × Sweden
1 × USA
1 × United Kingdom
3 × France
Collaborated with:A.Shrivastava Y.Paek Y.Kim H.Lee D.Nguyen K.Han K.Choi Y.Jeong S.Seo R.Jeyapaul J.Lee J.Lee S.K.Mylavarapu S.Choudhuri T.Givargis J.W.Yoon J.Jung S.Park D.Cho
Talks about:memori (3) error (3) cgras (3) soft (3) file (3) base (3) architectur (2) perform (2) system (2) regist (2)
Person: Jongeun Lee
DBLP: Lee:Jongeun
Contributed to:
2015
2014
20132011201020092009Wrote 10 papers:
- DAC-2015-LeeNL #optimisation #performance
- Optimizing stream program performance on CGRA-based systems (HL, DN, JL), p. 6.
- LCTES-2014-LeeLLP #architecture #performance
- Improving performance of loops on DIAM-based VLIW architectures (JL, JL, JL, YP), pp. 135–144.
- DATE-2013-HanCL #compilation
- Compiling control-intensive loops for CGRAs with state-based full predication (KH, KC, JL), pp. 1579–1582.
- DATE-2013-LeeJS #architecture #hybrid #memory management #performance
- Fast shared on-chip memory architecture for efficient hybrid computing with CGRAs (JL, YJ, SS), pp. 1575–1578.
- DATE-2011-YoonLJPKPC #configuration management #embedded #incremental #named
- I2CRF: Incremental interconnect customization for embedded reconfigurable fabrics (JWY, JL, JJ, SP, YK, YP, DC), pp. 1346–1351.
- LCTES-2010-KimLSP #memory management #multi
- Operation and data mapping for CGRAs with multi-bank memory (YK, JL, AS, YP), pp. 17–26.
- LCTES-2010-ShrivastavaLJ #embedded #equation #fault
- Cache vulnerability equations for protecting data in embedded processor caches from soft errors (AS, JL, RJ), pp. 143–152.
- DATE-2009-LeeS #fault #static analysis
- Static analysis to mitigate soft errors in register files (JL, AS), pp. 1367–1372.
- DATE-2009-MylavarapuCSLG #file system #named
- FSAF: File system aware flash translation layer for NAND Flash Memories (SKM, SC, AS, JL, TG), pp. 399–404.
- LCTES-2009-LeeS #compilation #fault #optimisation
- A compiler optimization to reduce soft errors in register files (JL, AS), pp. 41–49.