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Travelled to:
3 × France
3 × Germany
4 × USA
Collaborated with:
F.Vahid A.Ghosh A.C.Nácul S.Choudhuri B.Miller H.M.Buini S.Peter J.Henkel R.L.Lysecky S.K.Mylavarapu A.Shrivastava J.Lee
Talks about:
system (9) physic (4) embed (4) cach (4) design (3) model (3) flash (3) use (3) mockup (2) explor (2)

Person: Tony Givargis

DBLP DBLP: Givargis:Tony

Contributed to:

DAC 20152015
DAC 20132013
DATE 20122012
DATE 20092009
SAC 20092009
DATE 20052005
DATE v2 20042004
DAC 20032003
DATE 20032003
DATE 20002000

Wrote 12 papers:

DAC-2015-BuiniPG #automation #cyber-physical #design #modelling #physics #variability
Including variability of physical models into the design automation of cyber-physical systems (HMB, SP, TG), p. 6.
DAC-2013-MillerVG #modelling #physics #statistics #using
Exploration with upgradeable models using statistical methods for physical model emulation (BM, FV, TG), p. 6.
DATE-2012-MillerVG #automation #cyber-physical #mockup #named #testing #using
MEDS: Mockup Electronic Data Sheets for automated testing of cyber-physical systems using digital mockups (BM, FV, TG), pp. 1417–1420.
DATE-2009-MylavarapuCSLG #file system #named
FSAF: File system aware flash translation layer for NAND Flash Memories (SKM, SC, AS, JL, TG), pp. 399–404.
SAC-2009-ChoudhuriG #embedded #named #nondeterminism
FlashBox: a system for logging non-deterministic events in deployed embedded systems (SC, TG), pp. 1676–1682.
DATE-2005-GhoshG #distributed #locality #named #network #protocol #scheduling
LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling in Wireless Sensor Networks (AG, TG), pp. 190–195.
DATE-2005-NaculG #compilation #embedded #lightweight #multi #using
Lightweight Multitasking Support for Embedded Systems using the Phantom Serializing Compiler (ACN, TG), pp. 742–747.
DATE-v2-2004-NaculG #configuration management #power management
Dynamic Voltage and Cache Reconfiguration for Low Power (ACN, TG), pp. 1376–1379.
DAC-2003-Givargis #embedded #reduction
Improved indexing for cache miss reduction in embedded systems (TG), pp. 875–880.
DATE-2003-GhoshG #design #embedded
Analytical Design Space Exploration of Caches for Embedded Systems (AG, TG), pp. 10650–10655.
DATE-2000-HenkeGV #design #estimation #performance
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design (JH, TG, FV), pp. 333–338.
DATE-2000-LyseckyVG #latency
Techniques for Reducing Read Latency of Core Bus Wrappers (RLL, FV, TG), pp. 84–91.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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