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Travelled to:
2 × France
5 × Germany
8 × USA
Collaborated with:
S.Yoo Y.Shin D.Kim J.Jung J.Ahn K.Han J.Lee S.Park Y.Kim M.Kiemb Y.Cho J.Lee S.Park J.Yoo N.D.Dutt S.Y.Hwang T.Blank C.Park G.Lee N.Zergainoh M.Ahn J.W.Yoon Y.Paek K.Rha
Talks about:
architectur (5) reconfigur (4) schedul (4) system (4) power (4) grain (4) coars (4) time (4) processor (3) algorithm (3)

Person: Kiyoung Choi

DBLP DBLP: Choi:Kiyoung

Contributed to:

DAC 20142014
HPCA 20142014
DATE 20132013
DATE 20122012
DAC 20092009
DATE 20062006
DATE 20052005
DATE 20032003
LCTES 20032003
DATE 20012001
DAC 20002000
DATE 20002000
DAC 19991999
DAC 19971997
DAC 19881988

Wrote 16 papers:

DAC-2014-AhnYC #hybrid #memory management #power management
Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes (JA, SY, KC), p. 6.
HPCA-2014-AhnYC #architecture #named #predict
DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture (JA, SY, KC), pp. 25–36.
DATE-2013-HanCL #compilation
Compiling control-intensive loops for CGRAs with state-based full predication (KH, KC, JL), pp. 1579–1582.
DATE-2012-HanPC #architecture #configuration management #power management
State-based full predication for low power coarse-grained reconfigurable architecture (KH, SP, KC), pp. 1367–1372.
DAC-2009-YooYC #design #memory management #multi #performance
Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency (JhY, SY, KC), pp. 806–811.
DATE-2006-AhnYPKKC #algorithm #architecture #configuration management
A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures (MA, JWY, YP, YK, MK, KC), pp. 363–368.
DATE-2005-KimKPJC #architecture #configuration management #optimisation #pipes and filters #resource management
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization (YK, MK, CP, JJ, KC), pp. 12–17.
DATE-2003-ChoLYCZ #analysis #communication #design #scheduling
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design (YC, GL, SY, KC, NEZ), pp. 20132–20137.
LCTES-2003-LeeCD #algorithm #architecture #configuration management
An algorithm for mapping loops onto coarse-grained reconfigurable architectures (JeL, KC, NDD), pp. 183–188.
DATE-2001-JungYC #analysis #multi #performance
Performance improvement of multi-processor systems cosimulation based on SW analysis (JJ, SY, KC), pp. 749–753.
DAC-2000-ShinKC #analysis #embedded #multi #performance #realtime
Schedulability-driven performance analysis of multiple mode embedded real-time systems (YS, DK, KC), pp. 495–500.
DATE-2000-YooLJRCC #execution #performance
Fast Hardware-Software Coverification by Optimistic Execution of Real Processor (SY, JeL, JJ, KR, YC, KC), pp. 663–668.
DAC-1999-ParkC #scheduling
Performance-Driven Scheduling with Bit-Level Chaining (SP, KC), pp. 286–291.
DAC-1999-ShinC #realtime #scheduling
Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems (YS, KC), pp. 134–139.
DAC-1997-KimC #synthesis #using
Power-conscious High Level Synthesis Using Loop Folding (DK, KC), pp. 441–445.
DAC-1988-ChoiHB #algorithm #simulation
Incremental-in-time Algorithm for Digital Simulation (KC, SYH, TB), pp. 501–505.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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