Travelled to:1 × China
1 × USA
2 × Germany
3 × France
Collaborated with:K.Roy S.Bhunia H.Mahmoodi-Meimand G.Karakonstantis P.Vellanki K.S.Chatha R.Baldwin S.Bobovych R.Robucci C.Patel Q.Chen A.Datta S.Mukhopadhyay D.Chakraborty K.Dasgupta S.Mittal A.Joshi S.Nagar A.Rai S.Madan
Talks about:power (4) use (3) architectur (2) synthesi (2) process (2) pipelin (2) variat (2) model (2) dynam (2) gate (2)
Person: Nilanjan Banerjee
DBLP: Banerjee:Nilanjan
Contributed to:
2015
200920072006
200520052004Wrote 7 papers:
- DATE-2015-BaldwinBRPB #analysis #array #predict #using
- Gait analysis for fall prediction using hierarchical textile-based capacitive sensor arrays (RB, SB, RR, CP, NB), pp. 1293–1298.
- CIKM-2009-BanerjeeCDMJNRM #social #social media
- User interests in social media sites: an exploration with micro-blogs (NB, DC, KD, SM, AJ, SN, AR, SM), pp. 1823–1826.
- DATE-2007-BanerjeeKR #architecture #power management #process
- Process variation tolerant low power DCT architecture (NB, GK, KR), pp. 630–635.
- DATE-2006-BanerjeeRMB #fine-grained #logic #power management #synthesis #using
- Low power synthesis of dynamic logic circuits using fine-grained clock gating (NB, KR, HMM, SB), pp. 862–867.
- DAC-2005-BhuniaBCMR #approach #novel #power management #reduction #synthesis #using
- A novel synthesis approach for active leakage power reduction using dynamic supply gating (SB, NB, QC, HMM, KR), pp. 479–484.
- DATE-2005-DattaBMBR #design #modelling #pipes and filters #process #statistics
- Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies (AD, SB, SM, NB, KR), pp. 926–931.
- DATE-v2-2004-BanerjeeVC #architecture #performance
- A Power and Performance Model for Network-on-Chip Architectures (NB, PV, KSC), pp. 1250–1255.