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Travelled to:
1 × France
3 × Germany
5 × USA
Collaborated with:
K.Roy W.Yueh A.R.Trivedi S.Carlo S.Bhunia D.Kim M.F.Amir M.Cho A.Raychowdhury S.Ghosh K.Kim Q.Chen A.Bansal A.Agarwal C.H.Kim A.Datta N.Banerjee X.Wang D.B.Roy S.Narasimhan Y.Zheng D.Mukhopadhyay
Talks about:
power (7) design (6) scale (4) model (4) low (4) technolog (3) circuit (3) leakag (3) sram (3) nano (3)

Person: Saibal Mukhopadhyay

DBLP DBLP: Mukhopadhyay:Saibal

Contributed to:

DAC 20142014
DATE 20142014
DAC 20132013
DATE 20132013
DAC 20062006
DATE 20062006
DATE 20052005
DAC 20042004
DAC 20032003

Wrote 12 papers:

DAC-2014-KimM #3d #design #on the #reliability
On the Design of Reliable 3D-ICs Considering Charged Device Model ESD Events During Die Stacking (DK, SM), p. 6.
DATE-2014-TrivediAM #power management
Ultra-low power electronics with Si/Ge tunnel FET (ART, MFA, SM), pp. 1–6.
DAC-2013-CarloYM #3d #induction #integration #on the #power management
On the potential of 3D integration of inductive DC-DC converter for high-performance power delivery (SC, WY, SM), p. 8.
DAC-2013-TrivediCM #case study #power management
Exploring tunnel-FET for ultra low power analog applications: a case study on operational transconductance amplifier (ART, SC, SM), p. 6.
DAC-2013-WangYRNZMMB #design #grid #power management
Role of power grid in side channel attack and power-grid-aware secure design (XW, WY, DBR, SN, YZ, SM, DM, SB), p. 9.
DATE-2013-YuehCM #architecture #quality
Perceptual quality preserving SRAM architecture for color motion pictures (WY, MC, SM), pp. 103–108.
DAC-2006-GhoshMKR #power management #reduction #self
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM (SG, SM, KK, KR), pp. 971–976.
DATE-2006-ChenMBR #case study #design #power management
Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design (QC, SM, AB, KR), pp. 983–988.
DATE-2005-DattaBMBR #design #modelling #pipes and filters #process #statistics
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies (AD, SB, SM, NB, KR), pp. 926–931.
DATE-2005-MukhopadhyayBR #analysis #logic #modelling
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits (SM, SB, KR), pp. 224–229.
DAC-2004-AgarwalKMR #design
Leakage in nano-scale technologies: mechanisms, impact and design considerations (AA, CHK, SM, KR), pp. 6–11.
DAC-2003-MukhopadhyayRR #estimation #logic #modelling
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling (SM, AR, KR), pp. 169–174.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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