Travelled to:2 × France
3 × USA
Collaborated with:K.Kohno S.Mori J.Dao T.Hamai C.Ogawa Y.Watanabe K.Usami Y.Sugeno H.Hatada T.Kodaka S.Sasaki T.Kizu T.Tokuyoshi A.Takeda A.Yokosawa H.Xu T.Sano H.Usui J.Tanabe T.Miyamori R.Ohyama N.Nonogaki K.Kitayama T.Mori Y.Ueda H.Arakida Y.Okuda Y.Tsuboi
Talks about:processor (2) method (2) layout (2) core (2) methodolog (1) implement (1) transpar (1) datapath (1) consumpt (1) behavior (1)
Person: Nobu Matsumoto
DBLP: Matsumoto:Nobu
Contributed to:
20132009
200119931990Wrote 5 papers:
- DATE-2013-KodakaTSYKTXSUTMM #manycore #power management #predict
- A near-future prediction method for low power consumption on a many-core processor (TK, AT, SS, AY, TK, TT, HX, TS, HU, JT, TM, NM), pp. 1058–1059.
- DATE-2009-KodakaSTONKMUAOKTM #design #implementation #manycore #scalability #thread
- Design and implementation of scalable, transparent threads for multi-core media processor (TK, SS, TT, RO, NN, KK, TM, YU, HA, YO, TK, YT, NM), pp. 1035–1039.
- DAC-2001-KohnoM #behaviour #pipes and filters #verification
- A New Verification Methodology for Complex Pipeline Behavior (KK, NM), pp. 816–821.
- DAC-1993-DaoMHOM
- A Compaction Method for Full Chip VLSI Layouts (JD, NM, TH, CO, SM), pp. 407–412.
- DAC-1990-MatsumotoWUSHM #generative #layout
- Datapath Generator Based on Gate-Level Symbolic Layout (NM, YW, KU, YS, HH, SM), pp. 388–393.