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Travelled to:
1 × France
3 × USA
Collaborated with:
L.T.Pileggi X.Li A.Koorapaty V.Kheterpal Y.Xu P.Li M.Fu H.Schmit A.J.Strojwas C.Patel V.Rovner K.Y.Tong
Talks about:
regular (2) fabric (2) explor (2) architectur (1) placement (1) granular (1) frequenc (1) approach (1) perform (1) system (1)

Person: Padmini Gopalakrishnan

DBLP DBLP: Gopalakrishnan:Padmini

Contributed to:

DAC 20062006
DAC 20042004
DATE v1 20042004
DAC 20032003

Wrote 4 papers:

DAC-2006-GopalakrishnanLP #architecture #metric #using
Architecture-aware FPGA placement using metric embedding (PG, XL, LTP), pp. 460–465.
DAC-2004-LiXLGP #approach #simulation
A frequency relaxation approach for analog/RF system-level simulation (XL, YX, PL, PG, LTP), pp. 842–847.
DATE-v1-2004-KoorapatyKGFP #logic
Exploring Logic Block Granularity for Regular Fabrics (AK, VK, PG, MF, LTP), pp. 468–473.
DAC-2003-PileggiSSGKKPRT #trade-off
Exploring regular fabrics to optimize the performance-cost trade-off (LTP, HS, AJS, PG, VK, AK, CP, VR, KYT), pp. 782–787.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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