Travelled to:3 × USA
Collaborated with:A.J.Strojwas L.T.Pileggi V.Kheterpal T.Jhaveri T.G.Hersan D.Motiani Y.Takegawa H.Schmit P.Gopalakrishnan A.Koorapaty C.Patel K.Y.Tong
Talks about:regular (2) design (2) optim (2) lithographi (1) methodolog (1) manufactur (1) perform (1) fabric (1) explor (1) afford (1)
Person: Vyacheslav Rovner
DBLP: Rovner:Vyacheslav
Contributed to:
200920052003Wrote 3 papers:
- DAC-2009-StrojwasJRP #using
- Creating an affordable 22nm node using design-lithography co-optimization (AJS, TJ, VR, LTP), pp. 95–96.
- DAC-2005-KheterpalRHMTSP #design
- Design methodology for IC manufacturability based on regular logic-bricks (VK, VR, TGH, DM, YT, AJS, LTP), pp. 353–358.
- DAC-2003-PileggiSSGKKPRT #trade-off
- Exploring regular fabrics to optimize the performance-cost trade-off (LTP, HS, AJS, PG, VK, AK, CP, VR, KYT), pp. 782–787.