Travelled to:1 × France
1 × Germany
4 × USA
Collaborated with:L.T.Pileggi R.R.Taylor D.Whelihan V.Chandra A.Koorapaty C.Patel K.Y.Tong A.Xu C.Inacio D.Nagle A.Ryan D.E.Thomas Y.Tong B.Klass A.J.Strojwas P.Gopalakrishnan V.Kheterpal V.Rovner
Talks about:perform (2) fabric (2) optim (2) interconnect (1) architectur (1) methodolog (1) heterogen (1) benchmark (1) programm (1) regular (1)
Person: Herman Schmit
DBLP: Schmit:Herman
Contributed to:
2004
20042003200320021999Wrote 6 papers:
- DAC-2004-TaylorS #array #energy #performance
- Enabling energy efficiency in via-patterned gate array devices (RRT, HS), pp. 874–878.
- DATE-v2-2004-ChandraXSP #design #performance
- An Interconnect Channel Design Methodology for High Performance Integrated Circuits (VC, AX, HS, LTP), pp. 1138–1143.
- DAC-2003-PileggiSSGKKPRT #trade-off
- Exploring regular fabrics to optimize the performance-cost trade-off (LTP, HS, AJS, PG, VK, AK, CP, VR, KYT), pp. 782–787.
- DATE-2003-KoorapatyCTPPS #architecture #logic #programmable
- Heterogeneous Programmable Logic Block Architectures (AK, VC, KYT, CP, LTP, HS), pp. 11118–11119.
- DAC-2002-WhelihanS #memory management #network #optimisation
- Memory optimization in single chip network switch fabrics (DW, HS), pp. 530–535.
- DAC-1999-InacioSNRTTK #benchmark #metric
- Vertical Benchmarks for CAD (CI, HS, DN, AR, DET, YT, BK), pp. 408–413.