Travelled to:1 × France
1 × Germany
2 × USA
Collaborated with:A.Girault P.S.Roop F.Sagstetter P.Waszecki M.Lukasiewycz S.Chakraborty R.Sinha J.Reineke H.Stähle A.Knoll S.Steinhorst W.Chang M.Kauer P.Mundhenk S.Shreejith S.A.Fahmy
Talks about:architectur (2) analysi (2) time (2) multithread (1) determinist (1) framework (1) synchron (1) trigger (1) softwar (1) schedul (1)
Person: Sidharta Andalam
DBLP: Andalam:Sidharta
Contributed to:
20142013
20112010Wrote 5 papers:
- DAC-2014-SagstetterAWLSCK #architecture #framework #integration
- Schedule Integration Framework for Time-Triggered Automotive Architectures (FS, SA, PW, ML, HS, SC, AK), p. 6.
- DAC-2013-AndalamGSRR #analysis #precise
- Precise timing analysis for direct-mapped caches (SA, AG, RS, PSR, JR), p. 10.
- DAC-2013-LukasiewyczSASWCKMSFC #architecture #design
- System architecture and software design for electric vehicles (ML, SS, SA, FS, PW, WC, MK, PM, SS, SAF, SC), p. 6.
- DATE-2011-AndalamRG #analysis #source code
- Pruning infeasible paths for tight WCRT analysis of synchronous programs (SA, PSR, AG), pp. 204–209.
- DATE-2010-AndalamRG #multi #predict #thread #using
- Deterministic, predictable and light-weight multithreading using PRET-C (SA, PSR, AG), pp. 1653–1656.