Travelled to:2 × France
2 × USA
Collaborated with:E.Brockmeyer E.d.Greef S.Wuytack T.J.Ashby J.Ryckaert D.Verkest I.Karageorgos M.Stucchi P.Raghavan Z.Tokei S.Sakhare W.Dehaene A.Mallik P.Zuber T.Liu B.Chava B.Ballal P.R.D.Bario K.Croes M.Badaroglu A.Mercha
Talks about:interconnect (1) technolog (1) framework (1) systemat (1) platform (1) parallel (1) variabl (1) scratch (1) pattern (1) multipl (1)
Person: Rogier Baert
DBLP: Baert:Rogier
Contributed to:
2015
201320092008Wrote 4 papers:
- DATE-2015-KarageorgosSRRT #multi #variability
- Impact of interconnect multiple-patterning variability on SRAMs (IK, MS, PR, JR, ZT, DV, RB, SS, WD), pp. 609–612.
- DAC-2013-MallikZLCBBBCRBMV #analysis #evaluation #framework #named
- TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes (AM, PZ, TTL, BC, BB, PRDB, RB, KC, JR, MB, AM, DV), p. 6.
- DATE-2009-BaertBWA #using
- Exploring parallelizations of applications for MPSoC platforms using MPA (RB, EB, SW, TJA), pp. 1148–1153.
- DAC-2008-BaertGB #automation #case study #memory management
- An automatic scratch pad memory management tool and MPEG-4 encoder case study (RB, EdG, EB), pp. 201–204.