Travelled to:1 × France
2 × Germany
4 × USA
Collaborated with:S.Donnay G.G.E.Gielen H.D.Man P.Wambacq M.v.Heijningen M.Engels I.Bolsens G.V.d.Plas G.Decabooter F.Laulanet O.Charlier K.Tiri I.Verbauwhede G.Vandersteen P.Dobrovolný V.Gravot A.Mallik P.Zuber T.Liu B.Chava B.Ballal P.R.D.Bario R.Baert K.Croes J.Ryckaert A.Mercha D.Verkest
Talks about:substrat (5) nois (5) suppli (4) high (4) simul (3) level (3) digit (3) generat (2) circuit (2) reduct (2)
Person: Mustafa Badaroglu
DBLP: Badaroglu:Mustafa
Contributed to:
2013
200820042004200220012000Wrote 7 papers:
- DAC-2013-MallikZLCBBBCRBMV #analysis #evaluation #framework #named
- TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes (AM, PZ, TTL, BC, BB, PRDB, RB, KC, JR, MB, AM, DV), p. 6.
- DATE-2008-BadarogluDLC #using
- Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment (MB, GD, FL, OC), pp. 873–878.
- DAC-2004-PlasBVDWDGM #simulation
- High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects (GVdP, MB, GV, PD, PW, SD, GGEG, HDM), pp. 854–859.
- DATE-v1-2004-BadarogluWPDGM #reduction
- Digital Ground Bounce Reduction by Phase Modulation of the Clock (MB, PW, GVdP, SD, GGEG, HDM), pp. 88–93.
- DAC-2002-BadarogluTDWMVG #optimisation #reduction #using
- Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients (MB, KT, SD, PW, HDM, IV, GGEG), pp. 399–404.
- DATE-2001-BadarogluHGDMGEB #generative #multi #scalability #simulation
- High-level simulation of substrate noise generation from large digital circuits with multiple supplies (MB, MvH, VG, SD, HDM, GGEG, ME, IB), pp. 326–330.
- DAC-2000-HeijningenBDEB #generative #power management #simulation
- High-level simulation of substrate noise generation including power supply noise coupling (MvH, MB, SD, ME, IB), pp. 446–451.