BibSLEIGH
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
EDIT!
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
5 × USA
Collaborated with:
A.Majumdar Y.Lai K.C.Ho J.Pi C.P.Ravikumar A.C.Parker
Talks about:
placement (2) distribut (2) circuit (2) length (2) combin (2) test (2) architectur (1) transistor (1) floorplan (1) properti (1)

Person: Sarma Sastry

DBLP DBLP: Sastry:Sarma

Contributed to:

DAC 19921992
DAC 19911991
DAC 19891989
DAC 19881988
DAC 19841984

Wrote 7 papers:

DAC-1992-LaiS #diagrams #multi #verification
Edge-Valued Binary Decision Diagrams for Multi-Level Hierarchical Verification (YTL, SS), pp. 608–613.
DAC-1992-MajumdarS #fault #on the #random testing #testing
On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits (AM, SS), pp. 341–346.
DAC-1991-HoS #flexibility #matrix
Flexible Transistor Matrix (FTM) (KCH, SS), pp. 475–480.
DAC-1991-SastryM #analysis #branch #process
A Branching Process Model for Observability Analysis of Combinational Circuits (SS, AM), pp. 452–457.
DAC-1989-SastryP #clustering #problem #statistics
An Investigation into Statistical Properties of Partitioning and Floorplanning Problems (SS, JIP), pp. 382–387.
DAC-1988-KumarS #architecture #array #parallel
Parallel Placement on Reduced Array Architecture (CPR, SS), pp. 121–127.
DAC-1984-SastryP #logic #on the #slicing
On the relation between wire length distributions and placement of logic on master slice ICs (SS, ACP), pp. 710–711.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.